JP7052452B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 182
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 description 33
- 238000001514 detection method Methods 0.000 description 24
- 238000010586 diagram Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Description
図17に例示した半導体装置は、制御信号が入力される入力端子101、誘導性負荷を介して電源(車載の誘導性負荷であれば、バッテリ)に接続される出力端子102および接地端子103を有し、ローサイド型のスイッチング装置を構成している。この半導体装置では、パワー半導体素子104として、IGBT(Insulated Gate Bipolar Transistor)が使用されており、そのゲート端子は、入力端子101に接続されている。パワー半導体素子104のコレクタ端子は、出力端子102に接続され、エミッタ端子は、接地端子103に接続され、センスエミッタ端子は、センス抵抗105を介して接地端子103に接続されている。パワー半導体素子104のコレクタ端子とゲート端子との間には、2つのツェナーダイオードを逆直列に接続して構成されたアクティブクランプ回路106が接続されている。
また、アクティブクランプ回路のツェナーダイオードは、直列接続されて合計のツェナー電圧特性が第1のクランプ電圧に等しい第1のツェナーダイオードおよび第2のツェナーダイオードを有し、第1のツェナーダイオードおよび第2のツェナーダイオードの一方が第2のクランプ電圧に等しいツェナー電圧特性を有する。さらに、クランプ電圧切替回路は、第1のツェナーダイオードおよび第2のツェナーダイオードの直列回路に並列に接続された容量と抵抗または定電流素子との直列接続回路と、容量と抵抗または定電流素子との接続点の正方向の電圧変化を検出して第1のツェナーダイオードおよび第2のツェナーダイオードの他方の両端子を短絡するスイッチ素子とを有する。
図1は第1の実施の形態に係る半導体装置の内部構成例を示す回路図、図2はクランプ電圧およびその動作波形を示す図、図3はクランプ電圧とクランプ耐量との関係を示す図である。
図4は第2の実施の形態に係る半導体装置の要部構成例を示す回路図、図5は第2の実施の形態に係る半導体装置の動作波形を示す図、図6は第2の実施の形態に係る半導体装置の素子構造を示す断面図である。なお、図4において、図1に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。また、図4では、図1に示した半導体装置1から過熱検出回路17および過電流検出回路18を含む保護回路を省略し、制御回路16については、入力抵抗27だけを示している。
図7は第2の実施の形態に係る半導体装置の素子構造の変形例を示す断面図である。なお、図7において、図6に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。
図8は第3の実施の形態に係る半導体装置の要部構成例を示す回路図、図9は第3の実施の形態に係る半導体装置の動作波形を示す図、図10は第3の実施の形態に係る半導体装置の素子構造を示す断面図である。なお、図8において、図4に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。
図11は第4の実施の形態に係る半導体装置の要部構成例を示す回路図、図12は第4の実施の形態に係る半導体装置の素子構造を示す断面図である。なお、図11において、図4に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。
図13は第5の実施の形態に係る半導体装置の要部構成例を示す回路図、図14は第5の実施の形態に係る半導体装置の素子構造を示す断面図である。なお、図13において、図8に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。
図15は第6の実施の形態に係る半導体装置の要部構成例を示す回路図、図16は第6の実施の形態に係る半導体装置の素子構造を示す断面図である。なお、図15において、図4に示した構成要素と同じまたは均等の構成要素については同じ符号を付してその詳細な説明は省略する。
さらに、上記の実施の形態では、パワー半導体素子14としてMOSFETを使用した場合について説明したが、パワー半導体素子14にIGBTおよびフリーホイリングダイオードを使用したものでもよい。
2 誘導性負荷
3 バッテリ
11 入力端子
12 出力端子
13 接地端子
14 パワー半導体素子
15 ボディダイオード
16 制御回路
17 過熱検出回路
18 過電流検出回路
19 スイッチ素子
20,21 抵抗
22 アクティブクランプ回路
23,23a,23a1,23a2,23b,23b1,23b2 ツェナーダイオード
24 ダイオード
25 クランプ電圧切替回路
26 定電流素子
27 入力抵抗
31 容量
32 抵抗
33,33a スイッチ素子
34 定電流素子
41 N型基板
Claims (9)
- 入力端子と、出力端子と、接地端子と、前記出力端子に第1の主端子が接続され、前記接地端子に第2の主端子が接続され、前記入力端子に入力された信号によってゲート端子が駆動されるパワー半導体素子と、前記ゲート端子と前記第1の主端子との間に逆直列に接続されたツェナーダイオードおよびダイオードを有するアクティブクランプ回路とを備えた半導体装置において、
前記出力端子の正方向の電圧変化が検出されていないときに前記アクティブクランプ回路の前記ツェナーダイオードによって決まるクランプ電圧を第1のクランプ電圧に設定し、前記正方向の電圧変化を検出したときには前記ツェナーダイオードによって決まる前記クランプ電圧を前記第1のクランプ電圧より低い第2のクランプ電圧に設定するクランプ電圧切替回路を備え、
前記アクティブクランプ回路の前記ツェナーダイオードは、直列接続されて合計のツェナー電圧特性が前記第1のクランプ電圧に等しい第1のツェナーダイオードおよび第2のツェナーダイオードを有し、前記第1のツェナーダイオードおよび前記第2のツェナーダイオードの一方が前記第2のクランプ電圧に等しいツェナー電圧特性を有し、
前記クランプ電圧切替回路は、前記第1のツェナーダイオードおよび前記第2のツェナーダイオードの直列回路に並列に接続された容量と抵抗または定電流素子との直列接続回路と、前記容量と前記抵抗または前記定電流素子との接続点の前記正方向の電圧変化を検出して前記第1のツェナーダイオードおよび前記第2のツェナーダイオードの他方の両端子を短絡するスイッチ素子とを有する、
半導体装置。 - 前記第1のツェナーダイオードまたは前記第2のツェナーダイオードは、複数個のツェナーダイオードを直列接続して構成される、請求項1に記載の半導体装置。
- 入力端子と、出力端子と、接地端子と、前記出力端子に第1の主端子が接続され、前記接地端子に第2の主端子が接続され、前記入力端子に入力された信号によってゲート端子が駆動されるパワー半導体素子と、前記ゲート端子と前記第1の主端子との間に逆直列に接続されたツェナーダイオードおよびダイオードを有するアクティブクランプ回路とを備えた半導体装置において、
前記出力端子の正方向の電圧変化が検出されていないときに前記アクティブクランプ回路の前記ツェナーダイオードによって決まるクランプ電圧を第1のクランプ電圧に設定し、前記正方向の電圧変化を検出したときには前記ツェナーダイオードによって決まる前記クランプ電圧を前記第1のクランプ電圧より低い第2のクランプ電圧に設定するクランプ電圧切替回路を備え、
前記アクティブクランプ回路の前記ツェナーダイオードは、直列接続されて合計のツェナー電圧特性が前記第1のクランプ電圧に等しい第1のツェナーダイオードおよび第2のツェナーダイオードを有し、前記第1のツェナーダイオードおよび前記第2のツェナーダイオードの一方が前記第2のクランプ電圧に等しいツェナー電圧特性を有し、
前記クランプ電圧切替回路は、前記パワー半導体素子の前記第1の主端子および前記第2の主端子に接続された容量と抵抗または定電流素子との直列接続回路と、前記容量と前記抵抗または前記定電流素子との接続点の前記正方向の電圧変化を検出して前記第1のツェナーダイオードおよび前記第2のツェナーダイオードの他方の両端子を短絡するスイッチ素子とを有する、
半導体装置。 - 前記パワー半導体素子および前記クランプ電圧切替回路は、N型基板に形成されている、請求項1または3記載の半導体装置。
- 前記容量は、前記N型基板に形成されたダイオードのpn接合容量で構成されている、請求項4記載の半導体装置。
- 前記容量は、前記N型基板に形成されたMOSFETのゲート-ソース間容量とゲート-ドレイン間容量との合成容量で構成されている、請求項4記載の半導体装置。
- 前記抵抗は、前記N型基板の上面に形成されたポリシリコン抵抗によって構成されている、請求項4記載の半導体装置。
- 前記定電流素子は、前記N型基板に形成されたデプレッション型のMOSFETのゲート端子とソース端子とを接続して構成されている、請求項4記載の半導体装置。
- 前記第1のクランプ電圧は、前記パワー半導体素子に逆並列に接続されたダイオードのブレークダウン電圧より低い値に設定された、請求項1記載の半導体装置。
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