JP7034031B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP7034031B2 JP7034031B2 JP2018144797A JP2018144797A JP7034031B2 JP 7034031 B2 JP7034031 B2 JP 7034031B2 JP 2018144797 A JP2018144797 A JP 2018144797A JP 2018144797 A JP2018144797 A JP 2018144797A JP 7034031 B2 JP7034031 B2 JP 7034031B2
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Description
実施の形態1に係る半導体装置について説明する。図1および図2に示すように、半導体装置SDVは、第1半導体チップSCP1および第2半導体チップSCP2を備えている。第1半導体チップSCP1および第2半導体チップSCP2のそれぞれは、リードフレームLFMに搭載されて、封止樹脂RENによって封止されている。
ここでは、第2インダクタSIDに対する第1インダクタFIDの配置のバリエーションの一例について説明する。
ここでは、第2インダクタSIDに対する第1インダクタFIDの配置のバリエーションの他の例について説明する。
ここでは、第1インダクタFIDと第2インダクタSIDとの沿面距離を確保することができる構造の一例について説明する。
ここでは、第1インダクタFIDと第2インダクタSIDとの沿面距離に加えて、第2インダクタSIDと第1半導体チップSCP1の端との沿面距離を確保することができる構造の一例について説明する。
ここでは、第1インダクタFIDと第2インダクタSIDとの沿面距離に加えて、第2インダクタSIDと第1半導体チップSCP1の端との沿面距離を確保することができる構造の他の例について説明する。
各実施の形態に係る半導体装置の変形例について説明する。上述した各実施の形態に係る半導体装置SDVでは、第1絶縁体DTI1の幅と第2絶縁体DTI2の幅とが同じ幅W1の場合を例に挙げて説明した。第1絶縁体DTI1の幅と第2絶縁体DTI2の幅とは、必ずしも同じ幅である必要はなく、異なっていてもよい。
Claims (14)
- 半導体基板と、
前記半導体基板を覆うように形成された多層配線構造と、
第1電圧で駆動する第1回路と、
前記第1電圧よりも高い第2電圧で駆動する第2回路と、
前記第1回路に電気的に接続された第1インダクタと、
前記第2回路に電気的に接続された第2インダクタと
を備え、
前記多層配線構造は、
複数の配線と、
複数の前記配線を互いに電気的に絶縁する複数の層間絶縁膜と
を含み、
前記第1インダクタは、複数の前記層間絶縁膜のうち、第1層間絶縁膜内に形成され、
前記第2インダクタは、複数の前記層間絶縁膜のうち、前記第1層間絶縁膜とは異なる第2層間絶縁膜内に形成され、
平面視において、前記第1インダクタと前記第2インダクタとは、互いに重ならないように配置されているとともに、互いに沿うように配置されている、半導体装置。 - 前記半導体基板は、前記第1インダクタおよび前記第2インダクタの下方に配置され、
平面視において、前記第1インダクタと重なるように、前記半導体基板に形成された第1絶縁体と、
平面視において、前記第2インダクタと重なるように、前記半導体基板に形成された第2絶縁体と
を備えた、請求項1記載の半導体装置。 - 前記半導体基板に形成された、前記第1回路が形成された第1素子領域を規定する素子分離絶縁膜を含み、
前記第1絶縁体および前記第2絶縁体は、前記半導体基板の表面から、前記素子分離絶縁膜の底よりも深い位置にわたり形成された、請求項2記載の半導体装置。 - 前記半導体基板は、前記第1インダクタおよび前記第2インダクタの下方に配置され、
複数の前記層間絶縁膜のうち一の層間絶縁膜の表面に接するように、前記第1インダクタおよび前記第2インダクタのうちの少なくともいずれか一方が形成された、請求項1記載の半導体装置。 - 前記第2インダクタよりも外側に位置する前記一の層間絶縁膜の第3部分の表面は、前記第2インダクタが位置する前記一の層間絶縁膜の第4部分の表面よりも、前記半導体基板の表面に近い、請求項4記載の半導体装置。
- 前記多層配線構造では、
前記一の層間絶縁膜の表面に接するように前記第2インダクタが形成され、
複数の前記層間絶縁膜のうち、前記一の層間絶縁膜に対して、前記半導体基板側に位置する他の層間絶縁膜の表面に接するように、前記第1インダクタが形成された、請求項4記載の半導体装置。 - 前記第1インダクタおよび前記第2インダクタの形状は、平面視において、環形状である、請求項1記載の半導体装置。
- 前記半導体基板は、前記第1インダクタおよび前記第2インダクタの下方に配置され、
前記第1インダクタおよび前記第2インダクタは、平面視において、前記半導体基板の外縁部に沿うように延在している、請求項1記載の半導体装置。 - 半導体基板を用意する工程と、
前記半導体基板の主面に、第1素子領域および第2素子領域をそれぞれ規定する工程と、
前記第1素子領域に第1電圧で駆動する第1回路を形成し、前記第2素子領域に前記第1電圧よりも高い第2電圧で駆動する第2回路を形成する工程と、
前記第1回路および前記第2回路を覆うように、前記半導体基板上に複数の配線および複数の前記配線のそれぞれを電気的に絶縁する複数の層間絶縁膜を順次形成して多層配線構造を形成することにより、前記第1回路を含む第1半導体チップと、前記第2回路を含む第2半導体チップとを形成する工程と
を備え、
前記多層配線構造を形成する工程は、
前記第1半導体チップとなる領域に、前記第1回路に電気的に接続される第1インダクタを形成する工程と、
前記第1半導体チップとなる領域に、前記第2回路に電気的に接続される第2インダクタを形成する工程と
を含み、
前記第1インダクタを形成する工程および前記第2インダクタを形成する工程では、平面視において、前記第1インダクタと前記第2インダクタとは、互いに重ならないように形成されるとともに、互いに沿うように形成され、
前記多層配線構造を形成する工程は、
前記半導体基板を覆うように、複数の前記層間絶縁膜のうち一の層間絶縁膜を形成する工程と、
前記一の層間絶縁膜の表面に、前記第1インダクタおよび前記第2インダクタの少なくともいずれか一方を形成する工程と
を含み、
前記多層配線構造を形成する工程は、
前記一の層間絶縁膜を形成する前に、前記半導体基板を覆うように、複数の前記層間絶縁膜のうち他の層間絶縁膜を形成する工程と、
前記他の層間絶縁膜の表面に接するように前記第1インダクタを形成する工程と
を含む、半導体装置の製造方法。 - 前記第1インダクタの直下に位置することになる前記半導体基板の部分に、第1絶縁体を形成する工程と、
前記第2インダクタの直下に位置することになる前記半導体基板の部分に、第2絶縁体を形成する工程と
を含む、請求項9記載の半導体装置の製造方法。 - 前記第1素子領域および前記第2素子領域をそれぞれ規定する工程は、前記半導体基板に素子分離絶縁膜を形成する工程を含み、
前記第1絶縁体および前記第2絶縁体を形成する工程は、前記第1絶縁体および前記第2絶縁体を、前記半導体基板の前記主面から、前記素子分離絶縁膜の底よりも深い位置にわたり形成する工程を含む、請求項10記載の半導体装置の製造方法。 - 前記多層配線構造を形成する工程は、前記第2インダクタよりも外周側に位置する前記一の層間絶縁膜の第3部分に加工を施すことにより、前記一の層間絶縁膜の前記第3部分の表面を、前記第2インダクタが位置する前記一の層間絶縁膜の第4部分の表面に対して、前記半導体基板の側に後退させる部分を形成する工程を含む、請求項9記載の半導体装置の製造方法。
- 前記多層配線構造を形成する工程は、複数の前記配線のうち最上層に位置することになる最上層配線を、前記一の層間絶縁膜の表面に接するように形成する工程を含む、請求項9記載の半導体装置の製造方法。
- 前記半導体基板を用意する工程では、第1半導体基板と第2半導体基板とが用意され、
前記第1素子領域および前記第2素子領域をそれぞれ規定する工程では、
前記第1素子領域は、前記主面として前記第1半導体基板の第1主面に規定され、
前記第2素子領域は、前記主面として前記第2半導体基板の第2主面に規定され、
前記第1半導体チップおよび前記第2半導体チップを形成する工程では、
前記第1半導体チップは前記第1半導体基板に形成され、
前記第2半導体チップは前記第2半導体基板に形成される、請求項9記載の半導体装置の製造方法。
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