JP7008907B2 - 複数の材料を有する層を用いて基板をパターニングする方法 - Google Patents

複数の材料を有する層を用いて基板をパターニングする方法 Download PDF

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JP7008907B2
JP7008907B2 JP2018561727A JP2018561727A JP7008907B2 JP 7008907 B2 JP7008907 B2 JP 7008907B2 JP 2018561727 A JP2018561727 A JP 2018561727A JP 2018561727 A JP2018561727 A JP 2018561727A JP 7008907 B2 JP7008907 B2 JP 7008907B2
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Prior art keywords
etching
mandrel
substrate
layer
etching mask
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Japanese (ja)
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JP2019517154A5 (https=
JP2019517154A (ja
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ジェイ． デヴィリアーズ，アントン
モハンティ，ニハール
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4083—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
JP2018561727A 2016-05-23 2017-05-17 複数の材料を有する層を用いて基板をパターニングする方法 Active JP7008907B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662340279P 2016-05-23 2016-05-23
US62/340,279 2016-05-23
PCT/US2017/033051 WO2017205136A1 (en) 2016-05-23 2017-05-17 Method for patterning a substrate using a layer with multiple materials

Publications (3)

Publication Number Publication Date
JP2019517154A JP2019517154A (ja) 2019-06-20
JP2019517154A5 JP2019517154A5 (https=) 2020-06-25
JP7008907B2 true JP7008907B2 (ja) 2022-01-25

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JP2018561727A Active JP7008907B2 (ja) 2016-05-23 2017-05-17 複数の材料を有する層を用いて基板をパターニングする方法

Country Status (7)

Country Link
US (1) US10366890B2 (https=)
JP (1) JP7008907B2 (https=)
KR (1) KR102296805B1 (https=)
CN (1) CN109155238B (https=)
SG (1) SG11201810373YA (https=)
TW (1) TWI657484B (https=)
WO (1) WO2017205136A1 (https=)

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US11127594B2 (en) * 2017-12-19 2021-09-21 Tokyo Electron Limited Manufacturing methods for mandrel pull from spacers for multi-color patterning
US10366917B2 (en) 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
KR102617139B1 (ko) * 2018-04-09 2023-12-26 삼성전자주식회사 반도체 소자 및 그 제조방법
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US11061315B2 (en) * 2018-11-15 2021-07-13 Globalfoundries U.S. Inc. Hybrid optical and EUV lithography
US10529570B1 (en) * 2018-11-20 2020-01-07 Nanya Technology Corporation Method for preparing a semiconductor structure
US11069564B2 (en) * 2019-04-09 2021-07-20 International Business Machines Corporation Double metal patterning
CN110289221B (zh) * 2019-06-25 2021-06-29 武汉新芯集成电路制造有限公司 一种半导体器件及其制造方法
US11335566B2 (en) * 2019-07-19 2022-05-17 Tokyo Electron Limited Method for planarization of spin-on and CVD-deposited organic films
EP3840034B1 (en) 2019-12-19 2022-06-15 Imec VZW Method for producing nanoscaled electrically conductive lines for semiconductor devices
CN111162447B (zh) * 2019-12-31 2021-06-15 苏州辰睿光电有限公司 一种电极窗口、具有电极窗口的半导体器件的制作方法
WO2022235475A1 (en) * 2021-05-03 2022-11-10 Tokyo Electron Limited Wet-dry bilayer resist
KR20240056508A (ko) * 2021-08-25 2024-04-30 제미나티오, 인코포레이티드 내로우 라인 컷 마스킹 프로세스
US12211696B2 (en) * 2022-08-29 2025-01-28 Nanya Technology Corporation Method of manufacturing semiconductor structure with improved etching process
US12451354B2 (en) 2022-09-09 2025-10-21 Tokyo Electron Limited Double patterning method of patterning a substrate

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WO2009150870A1 (ja) 2008-06-13 2009-12-17 東京エレクトロン株式会社 半導体装置の製造方法
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WO2009150870A1 (ja) 2008-06-13 2009-12-17 東京エレクトロン株式会社 半導体装置の製造方法
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Also Published As

Publication number Publication date
TW201812847A (zh) 2018-04-01
KR20190000918A (ko) 2019-01-03
TWI657484B (zh) 2019-04-21
CN109155238B (zh) 2023-04-21
KR102296805B1 (ko) 2021-08-31
WO2017205136A1 (en) 2017-11-30
CN109155238A (zh) 2019-01-04
JP2019517154A (ja) 2019-06-20
SG11201810373YA (en) 2018-12-28
US10366890B2 (en) 2019-07-30
US20170338116A1 (en) 2017-11-23

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