SG11201810373YA - Method for patterning a substrate using a layer with multiple materials - Google Patents

Method for patterning a substrate using a layer with multiple materials

Info

Publication number
SG11201810373YA
SG11201810373YA SG11201810373YA SG11201810373YA SG11201810373YA SG 11201810373Y A SG11201810373Y A SG 11201810373YA SG 11201810373Y A SG11201810373Y A SG 11201810373YA SG 11201810373Y A SG11201810373Y A SG 11201810373YA SG 11201810373Y A SG11201810373Y A SG 11201810373YA
Authority
SG
Singapore
Prior art keywords
international
materials
ho1l
pct
self
Prior art date
Application number
SG11201810373YA
Other languages
English (en)
Inventor
Anton J Devilliers
Nihar Mohanty
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of SG11201810373YA publication Critical patent/SG11201810373YA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4083—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
SG11201810373YA 2016-05-23 2017-05-17 Method for patterning a substrate using a layer with multiple materials SG11201810373YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662340279P 2016-05-23 2016-05-23
PCT/US2017/033051 WO2017205136A1 (en) 2016-05-23 2017-05-17 Method for patterning a substrate using a layer with multiple materials

Publications (1)

Publication Number Publication Date
SG11201810373YA true SG11201810373YA (en) 2018-12-28

Family

ID=60330321

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201810373YA SG11201810373YA (en) 2016-05-23 2017-05-17 Method for patterning a substrate using a layer with multiple materials

Country Status (7)

Country Link
US (1) US10366890B2 (https=)
JP (1) JP7008907B2 (https=)
KR (1) KR102296805B1 (https=)
CN (1) CN109155238B (https=)
SG (1) SG11201810373YA (https=)
TW (1) TWI657484B (https=)
WO (1) WO2017205136A1 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018075755A1 (en) * 2016-10-20 2018-04-26 Tokyo Electron Limited Method of reducing overlay error in via to grid patterning
US11901190B2 (en) * 2017-11-30 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning
US11127594B2 (en) * 2017-12-19 2021-09-21 Tokyo Electron Limited Manufacturing methods for mandrel pull from spacers for multi-color patterning
US10366917B2 (en) 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
KR102617139B1 (ko) * 2018-04-09 2023-12-26 삼성전자주식회사 반도체 소자 및 그 제조방법
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US11061315B2 (en) * 2018-11-15 2021-07-13 Globalfoundries U.S. Inc. Hybrid optical and EUV lithography
US10529570B1 (en) * 2018-11-20 2020-01-07 Nanya Technology Corporation Method for preparing a semiconductor structure
US11069564B2 (en) * 2019-04-09 2021-07-20 International Business Machines Corporation Double metal patterning
CN110289221B (zh) * 2019-06-25 2021-06-29 武汉新芯集成电路制造有限公司 一种半导体器件及其制造方法
US11335566B2 (en) * 2019-07-19 2022-05-17 Tokyo Electron Limited Method for planarization of spin-on and CVD-deposited organic films
EP3840034B1 (en) 2019-12-19 2022-06-15 Imec VZW Method for producing nanoscaled electrically conductive lines for semiconductor devices
CN111162447B (zh) * 2019-12-31 2021-06-15 苏州辰睿光电有限公司 一种电极窗口、具有电极窗口的半导体器件的制作方法
WO2022235475A1 (en) * 2021-05-03 2022-11-10 Tokyo Electron Limited Wet-dry bilayer resist
KR20240056508A (ko) * 2021-08-25 2024-04-30 제미나티오, 인코포레이티드 내로우 라인 컷 마스킹 프로세스
US12211696B2 (en) * 2022-08-29 2025-01-28 Nanya Technology Corporation Method of manufacturing semiconductor structure with improved etching process
US12451354B2 (en) 2022-09-09 2025-10-21 Tokyo Electron Limited Double patterning method of patterning a substrate

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100691492B1 (ko) * 2005-09-29 2007-03-09 주식회사 하이닉스반도체 플래시 메모리 소자의 금속배선 형성방법
KR100744683B1 (ko) * 2006-02-27 2007-08-01 주식회사 하이닉스반도체 반도체 소자 제조 방법
KR100771891B1 (ko) * 2006-11-10 2007-11-01 삼성전자주식회사 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법
KR100825796B1 (ko) * 2006-12-14 2008-04-28 삼성전자주식회사 매몰 게이트를 구비한 반도체 소자의 제조 방법
US8838082B2 (en) 2008-11-26 2014-09-16 Ringcentral, Inc. Centralized status server for call management of location-aware mobile devices
US8600391B2 (en) 2008-11-24 2013-12-03 Ringcentral, Inc. Call management for location-aware mobile devices
US8670545B2 (en) 2007-09-28 2014-03-11 Ringcentral, Inc. Inbound call identification and management
US20090130854A1 (en) * 2007-11-21 2009-05-21 Macronix International Co., Ltd. Patterning structure and method for semiconductor devices
WO2009150870A1 (ja) * 2008-06-13 2009-12-17 東京エレクトロン株式会社 半導体装置の製造方法
US7915105B2 (en) * 2008-11-06 2011-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a metal gate
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
KR100995142B1 (ko) * 2008-12-22 2010-11-18 주식회사 하이닉스반도체 반도체소자의 컨택홀 형성방법
JP2011165933A (ja) * 2010-02-10 2011-08-25 Toshiba Corp 半導体装置の製造方法
JP2014072226A (ja) * 2012-09-27 2014-04-21 Tokyo Electron Ltd パターン形成方法
JP5983322B2 (ja) * 2012-11-05 2016-08-31 大日本印刷株式会社 パターン構造体の形成方法
US9362133B2 (en) * 2012-12-14 2016-06-07 Lam Research Corporation Method for forming a mask by etching conformal film on patterned ashable hardmask
US8828876B2 (en) 2013-01-09 2014-09-09 International Business Machines Corporation Dual mandrel sidewall image transfer processes
US9006804B2 (en) * 2013-06-06 2015-04-14 United Microelectronics Corp. Semiconductor device and fabrication method thereof
TWI531032B (zh) * 2013-11-21 2016-04-21 力晶科技股份有限公司 記憶體線路結構以及其半導體線路製程
US9209076B2 (en) 2013-11-22 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of double patterning lithography process using plurality of mandrels for integrated circuit applications
WO2015126829A1 (en) * 2014-02-23 2015-08-27 Tokyo Electron Limited Method for patterning a substrate for planarization
US9508713B2 (en) 2014-03-05 2016-11-29 International Business Machines Corporation Densely spaced fins for semiconductor fin field effect transistors
US9123656B1 (en) 2014-05-13 2015-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Organosilicate polymer mandrel for self-aligned double patterning process
FR3025937B1 (fr) * 2014-09-16 2017-11-24 Commissariat Energie Atomique Procede de grapho-epitaxie pour realiser des motifs a la surface d'un substrat
US9780193B2 (en) * 2015-10-27 2017-10-03 United Microelectronics Corporation Device with reinforced metal gate spacer and method of fabricating

Also Published As

Publication number Publication date
TW201812847A (zh) 2018-04-01
KR20190000918A (ko) 2019-01-03
JP7008907B2 (ja) 2022-01-25
TWI657484B (zh) 2019-04-21
CN109155238B (zh) 2023-04-21
KR102296805B1 (ko) 2021-08-31
WO2017205136A1 (en) 2017-11-30
CN109155238A (zh) 2019-01-04
JP2019517154A (ja) 2019-06-20
US10366890B2 (en) 2019-07-30
US20170338116A1 (en) 2017-11-23

Similar Documents

Publication Publication Date Title
SG11201810373YA (en) Method for patterning a substrate using a layer with multiple materials
SG11201806578XA (en) Self-alignment of metal and via using selective deposition
SG11201806451VA (en) Method and system for forming memory fin patterns
SG11201901207TA (en) Strip process for high aspect ratio structure
SG11201808546YA (en) Process and apparatus for processing a nitride structure without silica deposition
SG11201900319PA (en) Compositions and methods using same for carbon doped silicon containing films
SG11201906997XA (en) Contact passivation for perovskite optoelectronics
SG11201808337TA (en) Deactivation wipe kit and method of forming and using the same
SG11201901721RA (en) Optical device for enhancing human color vision
SG11201909897XA (en) Wafer scale bonded active photonics interposer
SG11201901210UA (en) Ferroelectric memory cells
SG11201810486VA (en) High resistivity single crystal silicon ingot and wafer having improved mechanical strength
SG11201809695TA (en) Modulators of the integrated stress pathway
SG11201907210YA (en) Policy communication via control plane signaling
SG11201808343WA (en) Dynamic cyclic prefix (cp) length in wireless communication
SG11201806216YA (en) Apparatus and method for encoding or decoding a multi-channel signal using a broadband alignment parameter and a plurality of narrowband alignment parameters
SG11201811336TA (en) Method for producing an electrode catalyst from a perovskite metal oxide
SG11201903228UA (en) Fabrication of filtration membranes
SG11201806553WA (en) Device and arrangement for controlling an electromagnetic wave, methods of forming and operating the same
SG11201901175YA (en) Cell rupture-based antimicrobial surfaces coated with metal oxide nano-arrays
SG11201809883QA (en) Fan-out wafer-level packaging method and the package produced thereof
SG11201808781TA (en) Coated glass surfaces and method for coating a glass substrate
SG11201804315TA (en) Monitoring traffic in a computer network ‎
SG11201906446RA (en) Removable temporary protective layers for use in semiconductor manufacturing
SG11201901873PA (en) Tablet compositions