JP6985366B2 - 低減された抵抗のために高アスペクト比電圧レールを採用する標準セル回路 - Google Patents

低減された抵抗のために高アスペクト比電圧レールを採用する標準セル回路 Download PDF

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JP6985366B2
JP6985366B2 JP2019503414A JP2019503414A JP6985366B2 JP 6985366 B2 JP6985366 B2 JP 6985366B2 JP 2019503414 A JP2019503414 A JP 2019503414A JP 2019503414 A JP2019503414 A JP 2019503414A JP 6985366 B2 JP6985366 B2 JP 6985366B2
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aspect ratio
high aspect
voltage rail
width
ratio voltage
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JP2019522376A (ja
JP2019522376A5 (https=
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ジェフリー・ジュンハオ・シュ
ムスタファ・バダログル
ダ・ヤン
ペリアンナン・チダンバラム
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Medicinal Preparation (AREA)
JP2019503414A 2016-07-27 2017-06-29 低減された抵抗のために高アスペクト比電圧レールを採用する標準セル回路 Active JP6985366B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662367230P 2016-07-27 2016-07-27
US62/367,230 2016-07-27
US15/634,039 US10090244B2 (en) 2016-07-27 2017-06-27 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
US15/634,039 2017-06-27
PCT/US2017/039870 WO2018022244A1 (en) 2016-07-27 2017-06-29 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

Publications (3)

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JP2019522376A JP2019522376A (ja) 2019-08-08
JP2019522376A5 JP2019522376A5 (https=) 2020-07-27
JP6985366B2 true JP6985366B2 (ja) 2021-12-22

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JP2019503414A Active JP6985366B2 (ja) 2016-07-27 2017-06-29 低減された抵抗のために高アスペクト比電圧レールを採用する標準セル回路

Country Status (9)

Country Link
US (1) US10090244B2 (https=)
EP (1) EP3491668B1 (https=)
JP (1) JP6985366B2 (https=)
KR (2) KR20190030686A (https=)
CN (2) CN109478551B (https=)
BR (1) BR112019001429B1 (https=)
SG (1) SG11201810982UA (https=)
TW (1) TWI742103B (https=)
WO (1) WO2018022244A1 (https=)

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US11205032B2 (en) * 2018-10-31 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design method, system and computer program product
EP3723127A1 (en) 2019-04-10 2020-10-14 IMEC vzw A standard cell device and a method for forming an interconnect structure for a standard cell device
US11444029B2 (en) 2020-02-24 2022-09-13 International Business Machines Corporation Back-end-of-line interconnect structures with varying aspect ratios
US11290109B1 (en) * 2020-09-23 2022-03-29 Qualcomm Incorporated Multibit multi-height cell to improve pin accessibility
US11778803B2 (en) * 2021-09-29 2023-10-03 Advanced Micro Devices, Inc. Cross FET SRAM cell layout
US12482746B2 (en) * 2021-10-22 2025-11-25 International Business Machines Corporation Early backside first power delivery network

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JP3917683B2 (ja) * 1996-04-25 2007-05-23 株式会社ルネサステクノロジ 半導体集積回路装置
US6838713B1 (en) 1999-07-12 2005-01-04 Virage Logic Corporation Dual-height cell with variable width power rail architecture
US6483131B1 (en) 2000-01-11 2002-11-19 Texas Instruments Incorporated High density and high speed cell array architecture
JP2002110805A (ja) 2000-09-28 2002-04-12 Toshiba Corp 半導体デバイス
JP2003303885A (ja) * 2002-04-08 2003-10-24 Mitsubishi Electric Corp 集積回路及びその設計方法
JP2004039724A (ja) * 2002-07-01 2004-02-05 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005136060A (ja) * 2003-10-29 2005-05-26 Yamaha Corp 半導体装置及びその製造方法
US9009641B2 (en) * 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
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US8102059B2 (en) * 2008-03-15 2012-01-24 Kabushiki Kaisha Toshiba Interconnect structure for high frequency signal transmissions
JP2009260158A (ja) * 2008-04-21 2009-11-05 Toshiba Corp 半導体集積回路装置における配線方法及び半導体集積回路装置
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JP2011082223A (ja) * 2009-10-02 2011-04-21 Renesas Electronics Corp 半導体集積回路装置
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US9337149B2 (en) * 2014-07-29 2016-05-10 Samsung Electronics Co, Ltd. Semiconductor devices and methods of fabricating the same
US10510688B2 (en) * 2015-10-26 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Via rail solution for high power electromigration

Also Published As

Publication number Publication date
CN118039636A (zh) 2024-05-14
US20180033729A1 (en) 2018-02-01
CN109478551A (zh) 2019-03-15
KR20230071197A (ko) 2023-05-23
KR102693848B1 (ko) 2024-08-08
TW201812873A (zh) 2018-04-01
EP3491668B1 (en) 2024-10-09
TWI742103B (zh) 2021-10-11
KR20190030686A (ko) 2019-03-22
BR112019001429A2 (https=) 2019-07-23
US10090244B2 (en) 2018-10-02
EP3491668A1 (en) 2019-06-05
BR112019001429B1 (pt) 2023-04-18
JP2019522376A (ja) 2019-08-08
EP3491668C0 (en) 2024-10-09
SG11201810982UA (en) 2019-02-27
CN109478551B (zh) 2024-03-26
WO2018022244A1 (en) 2018-02-01

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