KR20190030686A - 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들 - Google Patents

감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들 Download PDF

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KR20190030686A
KR20190030686A KR1020197000950A KR20197000950A KR20190030686A KR 20190030686 A KR20190030686 A KR 20190030686A KR 1020197000950 A KR1020197000950 A KR 1020197000950A KR 20197000950 A KR20197000950 A KR 20197000950A KR 20190030686 A KR20190030686 A KR 20190030686A
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South Korea
Prior art keywords
aspect ratio
high aspect
width
voltage rail
longitudinal axis
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Ceased
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KR1020197000950A
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English (en)
Korean (ko)
Inventor
제프리 준하오 수
무스타파 바다로그루
다 양
페리아난 치담바람
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퀄컴 인코포레이티드
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Priority to KR1020237016276A priority Critical patent/KR102693848B1/ko
Publication of KR20190030686A publication Critical patent/KR20190030686A/ko
Ceased legal-status Critical Current

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    • H01L27/0207—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G06F17/5072—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H01L21/76895—
    • H01L23/5283—
    • H01L23/5286—
    • H01L23/53252—
    • H01L23/53257—
    • H01L27/11807—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal
    • H01L2027/11881—

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Medicinal Preparation (AREA)
KR1020197000950A 2016-07-27 2017-06-29 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들 Ceased KR20190030686A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020237016276A KR102693848B1 (ko) 2016-07-27 2017-06-29 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662367230P 2016-07-27 2016-07-27
US62/367,230 2016-07-27
US15/634,039 US10090244B2 (en) 2016-07-27 2017-06-27 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
US15/634,039 2017-06-27
PCT/US2017/039870 WO2018022244A1 (en) 2016-07-27 2017-06-29 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020237016276A Division KR102693848B1 (ko) 2016-07-27 2017-06-29 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들

Publications (1)

Publication Number Publication Date
KR20190030686A true KR20190030686A (ko) 2019-03-22

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Application Number Title Priority Date Filing Date
KR1020197000950A Ceased KR20190030686A (ko) 2016-07-27 2017-06-29 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들
KR1020237016276A Active KR102693848B1 (ko) 2016-07-27 2017-06-29 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들

Family Applications After (1)

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KR1020237016276A Active KR102693848B1 (ko) 2016-07-27 2017-06-29 감소된 저항을 위해 고 종횡비 전압 레일들을 사용하는 표준 셀 회로들

Country Status (9)

Country Link
US (1) US10090244B2 (https=)
EP (1) EP3491668B1 (https=)
JP (1) JP6985366B2 (https=)
KR (2) KR20190030686A (https=)
CN (2) CN109478551B (https=)
BR (1) BR112019001429B1 (https=)
SG (1) SG11201810982UA (https=)
TW (1) TWI742103B (https=)
WO (1) WO2018022244A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11017146B2 (en) * 2018-07-16 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of forming the same
US11205032B2 (en) * 2018-10-31 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design method, system and computer program product
EP3723127A1 (en) 2019-04-10 2020-10-14 IMEC vzw A standard cell device and a method for forming an interconnect structure for a standard cell device
US11444029B2 (en) 2020-02-24 2022-09-13 International Business Machines Corporation Back-end-of-line interconnect structures with varying aspect ratios
US11290109B1 (en) * 2020-09-23 2022-03-29 Qualcomm Incorporated Multibit multi-height cell to improve pin accessibility
US11778803B2 (en) * 2021-09-29 2023-10-03 Advanced Micro Devices, Inc. Cross FET SRAM cell layout
US12482746B2 (en) * 2021-10-22 2025-11-25 International Business Machines Corporation Early backside first power delivery network

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3917683B2 (ja) * 1996-04-25 2007-05-23 株式会社ルネサステクノロジ 半導体集積回路装置
US6838713B1 (en) 1999-07-12 2005-01-04 Virage Logic Corporation Dual-height cell with variable width power rail architecture
US6483131B1 (en) 2000-01-11 2002-11-19 Texas Instruments Incorporated High density and high speed cell array architecture
JP2002110805A (ja) 2000-09-28 2002-04-12 Toshiba Corp 半導体デバイス
JP2003303885A (ja) * 2002-04-08 2003-10-24 Mitsubishi Electric Corp 集積回路及びその設計方法
JP2004039724A (ja) * 2002-07-01 2004-02-05 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005136060A (ja) * 2003-10-29 2005-05-26 Yamaha Corp 半導体装置及びその製造方法
US9009641B2 (en) * 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
CN100559576C (zh) * 2006-10-24 2009-11-11 株式会社电装 半导体器件
JP4535136B2 (ja) * 2008-01-17 2010-09-01 ソニー株式会社 半導体集積回路、および、スイッチの配置配線方法
US8102059B2 (en) * 2008-03-15 2012-01-24 Kabushiki Kaisha Toshiba Interconnect structure for high frequency signal transmissions
JP2009260158A (ja) * 2008-04-21 2009-11-05 Toshiba Corp 半導体集積回路装置における配線方法及び半導体集積回路装置
US7821039B2 (en) 2008-06-23 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Layout architecture for improving circuit performance
JP2011082223A (ja) * 2009-10-02 2011-04-21 Renesas Electronics Corp 半導体集積回路装置
US8212321B2 (en) * 2009-10-30 2012-07-03 Freescale Semiconductor, Inc. Semiconductor device with feedback control
US8336018B2 (en) 2010-06-09 2012-12-18 Lsi Corporation Power grid optimization
JP2012039073A (ja) * 2010-07-13 2012-02-23 Renesas Electronics Corp 半導体装置
US8513978B2 (en) 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US9026977B2 (en) 2013-08-16 2015-05-05 Globalfoundries Inc. Power rail layout for dense standard cell library
US9070552B1 (en) 2014-05-01 2015-06-30 Qualcomm Incorporated Adaptive standard cell architecture and layout techniques for low area digital SoC
US9887209B2 (en) * 2014-05-15 2018-02-06 Qualcomm Incorporated Standard cell architecture with M1 layer unidirectional routing
KR102310122B1 (ko) * 2014-06-10 2021-10-08 삼성전자주식회사 논리 셀 및 이를 포함하는 집적회로 소자와 논리 셀의 제조 방법 및 집적회로 소자의 제조 방법
US9337149B2 (en) * 2014-07-29 2016-05-10 Samsung Electronics Co, Ltd. Semiconductor devices and methods of fabricating the same
US10510688B2 (en) * 2015-10-26 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Via rail solution for high power electromigration

Also Published As

Publication number Publication date
CN118039636A (zh) 2024-05-14
US20180033729A1 (en) 2018-02-01
CN109478551A (zh) 2019-03-15
KR20230071197A (ko) 2023-05-23
KR102693848B1 (ko) 2024-08-08
TW201812873A (zh) 2018-04-01
EP3491668B1 (en) 2024-10-09
TWI742103B (zh) 2021-10-11
JP6985366B2 (ja) 2021-12-22
BR112019001429A2 (https=) 2019-07-23
US10090244B2 (en) 2018-10-02
EP3491668A1 (en) 2019-06-05
BR112019001429B1 (pt) 2023-04-18
JP2019522376A (ja) 2019-08-08
EP3491668C0 (en) 2024-10-09
SG11201810982UA (en) 2019-02-27
CN109478551B (zh) 2024-03-26
WO2018022244A1 (en) 2018-02-01

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