JP6972830B2 - 電界効果トランジスタの製造方法 - Google Patents
電界効果トランジスタの製造方法 Download PDFInfo
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- JP6972830B2 JP6972830B2 JP2017181482A JP2017181482A JP6972830B2 JP 6972830 B2 JP6972830 B2 JP 6972830B2 JP 2017181482 A JP2017181482 A JP 2017181482A JP 2017181482 A JP2017181482 A JP 2017181482A JP 6972830 B2 JP6972830 B2 JP 6972830B2
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- insulating film
- opening
- opening pattern
- resist mask
- resist
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- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
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Description
Claims (4)
- ゲート電極を備える電界効果トランジスタの製造方法であって、
基板上に成長した半導体層の表面を覆う絶縁膜を形成する工程と、
前記ゲート電極のための開口パターンを有するレジストマスクを前記絶縁膜上に形成する工程と、
前記開口パターンを介して前記絶縁膜をエッチングすることにより前記絶縁膜に凹部を形成する第1エッチング工程と、
前記レジストマスクを酸素プラズマに曝すことにより前記開口パターンの幅を広げる工程と、
前記レジストマスクを熱処理することにより前記開口パターンの側壁を傾斜させる工程と、
傾斜した前記開口パターンを介して前記レジストマスクの一部と前記絶縁膜とを更にエッチングすることにより、前記絶縁膜に当該絶縁膜の側壁が傾斜しており前記半導体層から離れるほど幅が広くなる開口を形成して前記半導体層の表面を露出させたのち、前記レジストマスクの残りを除去する第2エッチング工程と、
露出した前記半導体層の表面上、前記絶縁膜の開口の傾斜した側壁及び前記開口の周囲の前記絶縁膜上に前記ゲート電極を形成する工程と、
を含み、
前記開口パターンの側壁が傾斜する工程では、前記レジストマスクが流動することにより、前記開口パターンの側壁が傾斜し、前記開口パターンの側壁のうち前記絶縁膜に近い部分が前記開口パターンの内側に移動し、前記開口パターンが狭くなる、電界効果トランジスタの製造方法。 - 前記開口パターンの側壁を傾斜させる工程では、前記開口パターンの側壁の移動が前記凹部のエッジまでである、請求項1に記載の電界効果トランジスタの製造方法。
- 前記開口パターンの幅を広げる工程において、前記酸素プラズマは、前記開口パターンの幅を少なくとも5nm広げる、請求項1又は請求項2に記載の電界効果トランジスタの製造方法。
- 前記第1エッチング工程において、前記凹部の深さを少なくとも5nmとする、請求項1から請求項3のいずれか1項に記載の電界効果トランジスタの製造方法。
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