JP6972171B2 - レジストビアを有するファンアウトウエハレベルパッケージ - Google Patents

レジストビアを有するファンアウトウエハレベルパッケージ Download PDF

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JP6972171B2
JP6972171B2 JP2019555587A JP2019555587A JP6972171B2 JP 6972171 B2 JP6972171 B2 JP 6972171B2 JP 2019555587 A JP2019555587 A JP 2019555587A JP 2019555587 A JP2019555587 A JP 2019555587A JP 6972171 B2 JP6972171 B2 JP 6972171B2
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die
vias
package
carrier
layer
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JP2020517107A (ja
JP2020517107A5 (enExample
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ベルガセム ハーバ
イリアス モハメド
ラジェシュ カトカー
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インヴェンサス・コーポレイション
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2019555587A 2017-04-13 2018-04-11 レジストビアを有するファンアウトウエハレベルパッケージ Active JP6972171B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762484974P 2017-04-13 2017-04-13
US62/484,974 2017-04-13
US15/873,218 2018-01-17
US15/873,218 US10593563B2 (en) 2017-04-13 2018-01-17 Fan-out wafer level package with resist vias
PCT/US2018/027112 WO2018191380A1 (en) 2017-04-13 2018-04-11 Fan-out wafer level package with resist vias

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Publication Number Publication Date
JP2020517107A JP2020517107A (ja) 2020-06-11
JP2020517107A5 JP2020517107A5 (enExample) 2021-03-04
JP6972171B2 true JP6972171B2 (ja) 2021-11-24

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US (1) US10593563B2 (enExample)
JP (1) JP6972171B2 (enExample)
TW (1) TWI743351B (enExample)
WO (1) WO2018191380A1 (enExample)

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US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
KR102762976B1 (ko) 2020-01-03 2025-02-07 삼성전자주식회사 반도체 패키지
JP7574747B2 (ja) 2021-06-04 2024-10-29 株式会社デンソー 半導体装置およびその製造方法
KR20230141192A (ko) * 2022-03-31 2023-10-10 삼성전자주식회사 집적회로 소자의 제조 방법
CN115223973A (zh) * 2022-09-20 2022-10-21 盛合晶微半导体(江阴)有限公司 一种扇出型芯片封装结构及封装方法
CN117080087B (zh) * 2023-10-13 2024-02-13 季华实验室 一种扇出型板级封装方法及扇出型板级封装结构

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TW201842643A (zh) 2018-12-01
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