JP2020517107A5 - - Google Patents

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Publication number
JP2020517107A5
JP2020517107A5 JP2019555587A JP2019555587A JP2020517107A5 JP 2020517107 A5 JP2020517107 A5 JP 2020517107A5 JP 2019555587 A JP2019555587 A JP 2019555587A JP 2019555587 A JP2019555587 A JP 2019555587A JP 2020517107 A5 JP2020517107 A5 JP 2020517107A5
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JP
Japan
Prior art keywords
resist layer
layer
carrier
metal
die
Prior art date
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Granted
Application number
JP2019555587A
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English (en)
Japanese (ja)
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JP2020517107A (ja
JP6972171B2 (ja
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Priority claimed from US15/873,218 external-priority patent/US10593563B2/en
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Publication of JP2020517107A publication Critical patent/JP2020517107A/ja
Publication of JP2020517107A5 publication Critical patent/JP2020517107A5/ja
Application granted granted Critical
Publication of JP6972171B2 publication Critical patent/JP6972171B2/ja
Active legal-status Critical Current
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JP2019555587A 2017-04-13 2018-04-11 レジストビアを有するファンアウトウエハレベルパッケージ Active JP6972171B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762484974P 2017-04-13 2017-04-13
US62/484,974 2017-04-13
US15/873,218 2018-01-17
US15/873,218 US10593563B2 (en) 2017-04-13 2018-01-17 Fan-out wafer level package with resist vias
PCT/US2018/027112 WO2018191380A1 (en) 2017-04-13 2018-04-11 Fan-out wafer level package with resist vias

Publications (3)

Publication Number Publication Date
JP2020517107A JP2020517107A (ja) 2020-06-11
JP2020517107A5 true JP2020517107A5 (enExample) 2021-03-04
JP6972171B2 JP6972171B2 (ja) 2021-11-24

Family

ID=63790230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019555587A Active JP6972171B2 (ja) 2017-04-13 2018-04-11 レジストビアを有するファンアウトウエハレベルパッケージ

Country Status (4)

Country Link
US (1) US10593563B2 (enExample)
JP (1) JP6972171B2 (enExample)
TW (1) TWI743351B (enExample)
WO (1) WO2018191380A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
KR102762976B1 (ko) 2020-01-03 2025-02-07 삼성전자주식회사 반도체 패키지
JP7574747B2 (ja) 2021-06-04 2024-10-29 株式会社デンソー 半導体装置およびその製造方法
KR20230141192A (ko) * 2022-03-31 2023-10-10 삼성전자주식회사 집적회로 소자의 제조 방법
CN115223973A (zh) * 2022-09-20 2022-10-21 盛合晶微半导体(江阴)有限公司 一种扇出型芯片封装结构及封装方法
CN117080087B (zh) * 2023-10-13 2024-02-13 季华实验室 一种扇出型板级封装方法及扇出型板级封装结构

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US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
JP2006108211A (ja) 2004-10-01 2006-04-20 North:Kk 配線板と、その配線板を用いた多層配線基板と、その多層配線基板の製造方法
US8253230B2 (en) * 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
TWI501376B (zh) * 2009-10-07 2015-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
KR101059629B1 (ko) 2009-12-29 2011-08-25 하나 마이크론(주) 반도체 패키지 제조방법
US8922021B2 (en) * 2011-12-30 2014-12-30 Deca Technologies Inc. Die up fully molded fan-out wafer level packaging
US20110221018A1 (en) * 2010-03-15 2011-09-15 Xunqing Shi Electronic Device Package and Methods of Manufacturing an Electronic Device Package
JP5570855B2 (ja) * 2010-03-18 2014-08-13 新光電気工業株式会社 配線基板及びその製造方法並びに半導体装置及びその製造方法
KR101151258B1 (ko) 2010-04-13 2012-06-14 앰코 테크놀로지 코리아 주식회사 기준점 인식용 다이를 이용한 반도체 패키지 및 그 제조 방법
US8535980B2 (en) * 2010-12-23 2013-09-17 Stmicroelectronics Pte Ltd. Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package
CN102376672B (zh) 2011-11-30 2014-10-29 江苏长电科技股份有限公司 无基岛球栅阵列封装结构及其制造方法
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WO2016209207A1 (en) * 2015-06-22 2016-12-29 Intel Corporation Integrating mems structures with interconnects and vias
US9368450B1 (en) * 2015-08-21 2016-06-14 Qualcomm Incorporated Integrated device package comprising bridge in litho-etchable layer
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