JP6960908B2 - アレイ基板、アレイ基板の製造方法及び表示装置 - Google Patents
アレイ基板、アレイ基板の製造方法及び表示装置 Download PDFInfo
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- 238000005530 etching Methods 0.000 claims description 15
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- 230000000415 inactivating effect Effects 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000000428 dust Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000010292 electrical insulation Methods 0.000 description 4
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- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Description
12 パラレル信号線
13 タッチ電極
14 データ線
15 導電性残留物
20 基板
21 第1信号線
22 第2信号線
23 第3信号線
24 絶縁層
241 溝
251 ゲート電極
252 ゲート絶縁層
253 能動層
254 ソース電極
255 ドレイン電極
26 タッチ電極
27 不活性化層
28 画素電極
100 アレイ基板
200 アレイ基板
400 製造方法
500 製造方法
600 表示装置
Claims (9)
- タッチ表示装置用のアレイ基板であって、
基板と、
前記基板において、互いに分離して同一の層に配置される第1信号線および第2信号線と、
前記第1信号線および前記第2信号線を覆う絶縁層と、
前記第1信号線と前記第2信号線との間に位置し前記絶縁層を貫通する溝と、
前記絶縁層の上に配置された第3信号線と、
前記第3信号線の上に形成され、前記第3信号線に連結されるタッチ電極と、
を備えた、タッチ表示装置用のアレイ基板において、
前記基板における前記第3信号線の正投影が、前記基板における前記第1信号線の正投影と少なくとも部分的に重なって、前記第3信号線と前記第1信号線とは並列に連結されていることを特徴とする、タッチ表示装置用のアレイ基板。 - 前記基板における前記溝の投影はストリップで、
前記ストリップの延在方向は、前記第1信号線と前記第2信号線との間の空間領域の延在方向と同じまたは略同じで、
前記ストリップの延在方向に沿った前記ストリップの長さは、前記空間領域の延在方向に沿った前記空間領域の長さと同じまたは略同じであることを特徴とする請求項1に記載のタッチ表示装置用のアレイ基板。 - 前記第1信号線は前記第2信号線と並列に配置されることを特徴とする請求項1または2に記載のタッチ表示装置用のアレイ基板。
- 前記第2信号線はデータ線を含むことを特徴とする請求項3に記載のタッチ表示装置用のアレイ基板。
- タッチ表示装置用のアレイ基板の製造方法であって、
基板を用意するステップと、
前記基板において、互いに分離して同一の層に配置される第1信号線および第2信号線を含むパターンを形成するステップと、
前記第1信号線および前記第2信号線を覆う絶縁層を形成するステップと、
前記第1信号線と前記第2信号線との間に位置し前記絶縁層を貫通する溝を形成するステップと、を含み、
前記基板に前記第1信号線と前記第2信号線を含む前記パターンを形成した後に、前記第1信号線と前記第2信号線の間に導電性残留物が存在し、
当該製造方法は、前記溝を介しエッチングすることにより前記第1信号線と前記第2信号線の間にある前記導電性残留物を除去するステップと、
前記溝を形成した後、導電性材料層を形成するステップと、をさらに含み、
前記溝を介しエッチングすることにより前記導電性残留物を除去するステップが、
前記基板上の正投影が前記基板上の前記第1信号線の正投影と少なくとも部分的に重なるように導電性材料を前記導電性材料層の部分に保持し、第3信号線が形成されて前記導電性残留物が除去されるまで前記導電性材料層の他の部分の前記導電性材料をエッチングし、前記基板上の前記第3信号線の正投影が前記基板上の前記第1信号線の正投影と少なくとも部分的に重なるように、前記導電性材料層をパターニングするステップを含み、
当該製造方法は、前記導電性材料層をパターニングした後に、前記第3信号線の上にタッチ電極を含むパターンを形成するステップをさらに含み、
前記第3信号線は前記タッチ電極に連結され、
前記第3信号線と前記第1信号線とは並列に連結されていることを特徴とする、タッチ表示装置用のアレイ基板の製造方法。 - 前記溝を形成するステップは、前記基板における投影がストリップである溝を形成することを含み、
前記ストリップの延在方向は、前記第1信号線と前記第2信号線との間の空間領域の延長方向と同じまたは略同じで、
前記ストリップの延在方向に沿った前記ストリップの長さは、前記空間領域の延在方向に沿った前記空間領域の長さと同じまたは略同じであることを特徴とする請求項5に記載のタッチ表示装置用のアレイ基板の製造方法。 - 前記第1信号線は前記第2信号線と並列に形成されることを特徴とする請求項5に記載のタッチ表示装置用のアレイ基板の製造方法。
- 前記第2信号線はデータ線を含むことを特徴とする請求項7に記載のタッチ表示装置用のアレイ基板の製造方法。
- 請求項1に記載のタッチ表示装置用のアレイ基板を備えていることを特徴とする表示装置。
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CN201710123374.6 | 2017-03-03 | ||
CN201710123374.6A CN108536324B (zh) | 2017-03-03 | 2017-03-03 | 阵列基板及其制作方法、显示装置 |
PCT/CN2017/097471 WO2018157563A1 (en) | 2017-03-03 | 2017-08-15 | Array substrate, fabrication method and display device |
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EP (1) | EP3590030A4 (ja) |
JP (1) | JP6960908B2 (ja) |
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WO (1) | WO2018157563A1 (ja) |
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CN109460162B (zh) * | 2018-10-31 | 2022-05-24 | 上海天马微电子有限公司 | 一种触控显示面板以及电子设备 |
CN113744629B (zh) * | 2020-05-27 | 2023-01-31 | 群创光电股份有限公司 | 显示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100276225B1 (ko) * | 1998-06-01 | 2000-12-15 | 구본준 | 액정표시장치의 패드 단락 방지구조 및 그 방법 |
JP2002156755A (ja) * | 2000-11-20 | 2002-05-31 | Fuji Photo Film Co Ltd | 平版印刷版原版 |
JP3806629B2 (ja) * | 2001-09-28 | 2006-08-09 | 三洋電機株式会社 | 液晶表示装置 |
KR20070117738A (ko) * | 2006-06-09 | 2007-12-13 | 삼성전자주식회사 | 표시기판의 리페어 방법 및 이에 의해 리페어된 표시기판 |
WO2009078200A1 (ja) * | 2007-12-19 | 2009-06-25 | Sharp Kabushiki Kaisha | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機 |
US8388852B2 (en) * | 2010-07-30 | 2013-03-05 | Apple Inc. | Method for fabricating touch sensor panels |
CN201886234U (zh) * | 2010-11-29 | 2011-06-29 | 北京京东方光电科技有限公司 | 液晶显示基板和液晶显示器 |
WO2012077321A1 (ja) * | 2010-12-09 | 2012-06-14 | シャープ株式会社 | タッチパネル及びそれを備えた表示装置並びにタッチパネルの製造方法 |
JP2012155198A (ja) * | 2011-01-27 | 2012-08-16 | Seiko Epson Corp | 電気光学装置及び電子機器 |
CN103293803B (zh) * | 2012-12-26 | 2016-08-03 | 成都天马微电子有限公司 | 用于ffs模式液晶显示器的阵列基板及其制造方法 |
CN103186287B (zh) * | 2013-03-28 | 2015-12-23 | 合肥京东方光电科技有限公司 | 一种触控显示屏及触控显示装置 |
CN103927038B (zh) * | 2013-06-09 | 2017-08-29 | 上海天马微电子有限公司 | 一种内嵌式触摸屏及其电压检测方法 |
JP6375223B2 (ja) * | 2014-01-31 | 2018-08-15 | 株式会社ジャパンディスプレイ | センサ付表示装置及びその駆動方法 |
KR101633175B1 (ko) | 2014-04-29 | 2016-06-24 | 엘지디스플레이 주식회사 | 터치 센서 일체형 표시장치 |
CN104020913A (zh) * | 2014-05-30 | 2014-09-03 | 京东方科技集团股份有限公司 | 一种内嵌式触摸屏及显示装置 |
CN203858617U (zh) * | 2014-05-30 | 2014-10-01 | 京东方科技集团股份有限公司 | 一种阵列基板、电容式内嵌触摸屏 |
CN104951143B (zh) * | 2015-07-27 | 2020-05-08 | 京东方科技集团股份有限公司 | 一种阵列基板、触控面板及显示装置 |
CN105629613A (zh) * | 2016-03-17 | 2016-06-01 | 深圳市华星光电技术有限公司 | 显示面板的信号线制作方法 |
CN106057823B (zh) * | 2016-07-29 | 2019-05-10 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN106231787B (zh) * | 2016-09-22 | 2019-03-08 | 深圳市迅捷兴科技股份有限公司 | 电磁局部屏蔽的印制电路板结构及其制作方法 |
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- 2017-08-15 EP EP17835444.5A patent/EP3590030A4/en active Pending
- 2017-08-15 US US15/745,000 patent/US10545594B2/en active Active
- 2017-08-15 WO PCT/CN2017/097471 patent/WO2018157563A1/en unknown
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EP3590030A4 (en) | 2020-12-30 |
CN108536324A (zh) | 2018-09-14 |
US20190012023A1 (en) | 2019-01-10 |
JP2020512602A (ja) | 2020-04-23 |
EP3590030A1 (en) | 2020-01-08 |
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WO2018157563A1 (en) | 2018-09-07 |
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