JP6909430B2 - Manufacturing method of through electrode substrate, mounting substrate including through electrode substrate, and through electrode substrate - Google Patents

Description

The embodiments of the present disclosure relate to a through silicon via substrate including a through electrode. Further, the embodiment of the present disclosure relates to a mounting substrate provided with a through electrode substrate and a method for manufacturing the through electrode substrate.

A member including a substrate including the first surface and the second surface, a plurality of through holes provided in the substrate, and a through electrode located inside the through holes, a so-called through electrode substrate, is used for various purposes. ing.

For example, this through silicon via substrate is used as an interposer interposed between two LSI chips when stacking a plurality of LSI chips in order to increase the mounting density of LSIs. Further, the through silicon via substrate may be interposed between an element such as an LSI chip and a mounting substrate such as a motherboard.

Here, for example, Patent Document 1 discloses a technique relating to an interposer, in which a through hole is formed in a glass substrate by using a laser beam and the through hole is plated. Then, according to the method for manufacturing a glass substrate described in Patent Document 1, it is possible to form a tapered through hole in the glass substrate.

Further, Patent Document 2 discloses a technique relating to an interposer formed by forming a multilayer wiring layer on a glass substrate. This interposer forms an inorganic adhesion layer only inside the through hole, forms a conductive layer on the inorganic adhesion layer, and the conductive layer is electrically connected to a wiring group via a conductive via and is inorganic. The coefficient of thermal expansion of the adhesive layer is larger than the coefficient of thermal expansion of the base material and smaller than the coefficient of thermal expansion of the conductive layer. According to the interposer described in Patent Document 2, peeling of the conductive layer pattern due to thermal expansion and contraction can be prevented.

Japanese Unexamined Patent Publication No. 2014-139963 Japanese Unexamined Patent Publication No. 2015-198093

Here, in the inventions described in Patent Documents 1 and 2 described above, the point of forming a capacitor at a high density has not been sufficiently studied, and there is a concern that it will be difficult to increase the mounting density.

An object of the present disclosure is to provide a through electrode substrate, a mounting substrate including the through electrode substrate, and a method for manufacturing the through electrode substrate, which can effectively solve such a problem.

The through silicon via substrate according to the embodiment of the present disclosure is
An electrode through hole that includes a first surface and a second surface located on the opposite side of the first surface and penetrates between the first surface and the second surface, and the first surface and the second surface. A substrate provided with a through hole for a capacitor that penetrates between the surfaces,
A through electrode located in the electrode through hole of the substrate and
Over the vicinity of the first surface opening of the first surface of the capacitor through hole of the substrate, the side wall of the capacitor through hole, and the vicinity of the second surface opening of the second surface of the capacitor through hole. A capacitor that is continuously provided and has a laminated structure in which a first surface second electrode layer, a dielectric layer, and a first surface first electrode layer are laminated in this order is provided.

In the through electrode substrate
A wiring layer that electrically connects only one of the through electrode and the first surface second electrode layer or the first surface first electrode layer may be further provided.

In the through electrode substrate
The side end portion of the first surface second electrode layer on the first surface of the substrate may be covered with the dielectric layer on the first surface.

In the through electrode substrate
The side end portion of the dielectric layer on the first surface of the substrate is the first surface of the substrate so as to cover the end portion of the first surface second electrode layer on the first surface of the substrate. It may be located on the surface.

In the through electrode substrate
The side end portion of the first surface first electrode layer on the first surface of the substrate may be located on the side end portion of the dielectric layer on the first surface of the substrate. ..

In the through electrode substrate
The first surface second electrode layer may have a recess at the boundary between the side end portion of the first surface second electrode layer and the first surface of the substrate.

In the through electrode substrate
The film thickness of the first surface second electrode layer may be thicker than the film thickness of the first surface first electrode layer.

In the through electrode substrate
The width of the through hole for the electrode may be the same as the width of the through hole for the capacitor.

In the through electrode substrate
The width of the through hole for the electrode may be larger than the width of the through hole for the capacitor.

In the through electrode substrate
On the first surface side of the substrate, the first surface first electrode layer and the dielectric layer are penetrated, and the first surface first electrode layer is insulated from the first surface first electrode layer, and the first surface second electrode layer is formed. An electrically connected through-hole wiring may be further provided.

In the through electrode substrate
The substrate may be provided with a plurality of through holes for the capacitors, and the capacitors may be provided in a one-to-one correspondence with the through holes for each capacitor.

In the through electrode substrate
The first surface second electrode layer, the dielectric layer, and the first surface first electrode layer of the capacitor adjacent on the first surface of the substrate are continuous on the first surface of the substrate. It may be connected to the target.

In the through electrode substrate
The first surface second electrode layer, the dielectric layer, and the first surface first electrode layer of the capacitor adjacent on the first surface of the substrate are continuous on the first surface of the substrate. It may not be connected to the target.

In the through electrode substrate
The cross section of the through hole for the capacitor parallel to the first surface may be circular.

In the through electrode substrate
The through electrode may have a seed layer formed along the side wall of the through hole for the electrode and a plating layer formed on the surface of the seed layer.

In the through electrode substrate
The through electrode, the first surface conductive layer electrically connected to the through electrode and located on the first surface side, and the first surface conductive layer electrically connected to the through electrode and located on the second surface side. An inductor having a second surface conductive layer may be further provided.

The mounting board according to the embodiment of the present disclosure is
Through electrode substrate and
The element mounted on the through electrode substrate is provided.
The through electrode substrate is
A through hole including a first surface and a second surface located on the opposite side of the first surface, penetrating between the first surface and the second surface, and the first surface and the second surface. A substrate provided with a through hole for a capacitor that penetrates between them,
A through electrode located in the electrode through hole of the substrate and
Over the vicinity of the first surface opening of the first surface of the capacitor through hole of the substrate, the side wall of the capacitor through hole, and the vicinity of the second surface opening of the second surface of the capacitor through hole. A capacitor that is continuously provided and has a laminated structure in which a first surface second electrode layer, a dielectric layer, and a first surface first electrode layer are laminated in this order is provided.

The method for manufacturing the through silicon via substrate according to the embodiment of the present disclosure is as follows.
An electrode through hole that includes a first surface and a second surface located on the opposite side of the first surface and penetrates between the first surface and the second surface, and the first surface and the second surface. The process of preparing a substrate provided with a through hole for a capacitor that penetrates between the surfaces, and
A step of forming a through electrode located in the through hole for the electrode of the substrate, and
Over the vicinity of the first surface opening of the first surface of the capacitor through hole of the substrate, the side wall of the capacitor through hole, and the vicinity of the second surface opening of the second surface of the capacitor through hole. The present invention includes a step of forming a capacitor having a laminated structure which is continuously provided and has a laminated structure in which a first surface second electrode layer, a dielectric layer, and a first surface first electrode layer are laminated in this order.

In the method for manufacturing a through electrode substrate,
At the same time as forming the through electrode, the first surface and the second electrode layer of the capacitor may be formed.

According to the embodiment of the present disclosure, it is possible to provide a through electrode substrate provided with a through electrode and capable of mounting a capacitor at a high density.

FIG. 1 is a cross-sectional view showing a through electrode substrate according to an embodiment. FIG. 2 is a cross-sectional view showing a partially enlarged view of the vicinity of the through hole of the through electrode substrate shown in FIG. FIG. 3 is a cross-sectional view showing a partially enlarged through hole for a capacitor of the through electrode substrate shown in FIG. FIG. 4 is a plan view showing the through silicon via substrate shown in FIG. FIG. 5 is a diagram showing another example of the capacitor shown in FIG. FIG. 6 is a diagram showing still another example of the capacitor shown in FIG. FIG. 7 is a diagram showing an example of the configuration of the side end portion of the capacitor on the first surface of the through electrode substrate shown in FIG. FIG. 8 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG.

NS.
FIG. 9 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 10 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 11 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 12 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 13 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 14 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 15 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 16 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 17 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 18 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 19 is a diagram showing an example of a manufacturing process of the through silicon via substrate shown in FIG. 1, following FIG. FIG. 20 is a cross-sectional view showing an example of a mounting substrate including the through silicon via substrate and the element shown in FIG. FIG. 21 is a diagram showing an example of a product on which the through silicon via substrate shown in FIG. 1 is mounted.

Hereinafter, the configuration of the through silicon via substrate and the manufacturing method thereof according to the embodiment of the present disclosure will be described in detail with reference to the drawings. The embodiments shown below are examples of the embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in the present specification, terms such as "board", "base material", "sheet" and "film" are not distinguished from each other based only on the difference in names. For example, "base material" and "base material" are concepts including members that can be called sheets and films. Furthermore, the terms used in this specification, such as "parallel" and "orthogonal", and the values of length and angle, which specify the shape and geometric conditions and their degrees, are bound by a strict meaning. Instead, the interpretation will include the range in which similar functions can be expected. Further, in the drawings referred to in the present embodiment, the same parts or parts having similar functions are designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. In addition, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

Through Silicon Via Substrate Hereinafter, embodiments of the present disclosure will be described. First, the configuration of the through silicon via substrate 10 according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing the through silicon via substrate 10 according to the embodiment. Further, FIG. 2 is a cross-sectional view showing a partially enlarged view of the vicinity of the through hole of the through electrode substrate shown in FIG. Further, FIG. 3 is a cross-sectional view showing a partially enlarged through hole for a capacitor of the through electrode substrate shown in FIG. Further, FIG. 4 is a plan view showing the through silicon via substrate shown in FIG. Note that FIG. 4 schematically shows a cross section along the surface of the first surface first conductive layer 311 for the sake of simplicity.

The through electrode substrate 10 includes a substrate 12, a through electrode 22, a first wiring structure portion 30, and a second wiring structure portion 40. Hereinafter, each component of the through silicon via substrate 10 will be described.

(substrate)
The substrate 12 includes a first surface 13 and a second surface 14 located on the opposite side of the first surface 13.

Further, the substrate 12 is provided with a plurality of electrode through holes 20 extending from the first surface 13 to the second surface 14, that is, penetrating between the first surface 13 and the second surface 14.

Further, the substrate 12 has a plurality of through holes for capacitors that penetrate between the first surface 13 and the second surface 14 and have an opening Za on the first surface 13 and a second surface opening Zc on the second surface 14. Z is provided. In the example of FIG. 1, two through holes Z for capacitors are formed on the substrate 12, but one or more through holes Z for capacitors may be formed on the substrate 12. ..

As described above, in the example of FIG. 1, the substrate 12 is provided with a plurality of through holes Z for capacitors on the first surface 13, and the capacitors 15 are provided in a one-to-one correspondence with each through hole Z for capacitors. ..

The cross section of the through hole Z for the capacitor parallel to the first surface 13 is, for example, circular. However, the cross section of the through hole Z for the capacitor parallel to the first surface 13 may have a shape such as a quadrangle other than a circle.

Further, the substrate 12 contains an inorganic material having a certain insulating property. For example, the substrate 12 includes a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a glass epoxy substrate, a silicon substrate, an SOI (Silicon on Insulator) substrate, an SOS (Silicon on Sapphire), a silicon carbide (SiC) substrate, and an alumina (Al). _{A 2} O ₃ ) substrate, an aluminum nitride (AlN) substrate, a dilyconium oxide (ZrO ₂ ) substrate, or a substrate in which these are laminated can be used. The substrate 12 may partially include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate.

Examples of the glass used in the substrate 12 include non-alkali glass.

This non-alkali glass is glass that does not contain alkaline components such as sodium and potassium. Non-alkali glass contains, for example, boric acid instead of the alkaline component. The non-alkali glass also contains, for example, alkaline earth metal oxides such as calcium oxide and barium oxide. Examples of non-alkali glass include EN-A1 manufactured by Asahi Glass and Eagle XG manufactured by Corning. When the substrate 12 contains glass, the thickness of the substrate 12 is, for example, 0.10 mm or more and 0.40 mm or less. Since the substrate 12 contains glass, the insulating property of the substrate 12 can be improved. As a result, when the capacitor 15 is formed by a part of the first wiring structure portion 30 as described later, the withstand voltage characteristic of the capacitor 15 can be improved.

Further, although not shown, the side wall 21 of the through hole 20 for the electrode may extend along the normal direction of the first surface 13 of the substrate 12. Alternatively, the side wall 21 may extend in a direction deviated from the normal direction of the first surface 13 of the substrate 12, or a part of the side wall 21 may be curved.

Further, the length of the through hole 20 for the electrode, that is, the dimension of the through hole 20 for the electrode in the normal direction of the first surface 13 is equal to the thickness of the substrate 12. The width S of the electrode through hole 20, that is, the dimension of the electrode through hole 20 in the plane direction of the first surface 13 (see FIG. 8) is, for example, 40 μm or more and 150 μm or less. The ratio of the length of the through hole 20 for the electrode to the width S is, for example, 4 or more and 10 or less.

The width S of the through hole 20 for the electrode is, for example, the same size as the width a1 of the through hole Z for the capacitor shown in FIG. However, the width S of the through hole 20 for the electrode may be set to be larger than the width a1 of the through hole Z for the capacitor shown in FIG. 3, for example.

(Through silicon via)
The through electrode 22 is a member that is at least partially located inside the through hole 20 for the electrode and has conductivity.

In the present embodiment, the thickness of the through electrode 22 is smaller than the width of the through hole 20 for the electrode. Therefore, there is a space inside the through electrode 22 in which the through electrode 22 does not exist. That is, the through electrode 22 is a so-called conformal via.

Further, the through electrode 22 may be formed by a physical film forming method such as a vapor deposition method or a sputtering method, or may be formed by a chemical film forming method or a plating method. Further, the through electrode 22 may be composed of a single conductive layer, or may include a plurality of conductive layers.

Here, as shown in FIG. 2, an example in which the through electrode 22 includes an adhesion layer 361, a seed layer 362, and a plating layer 363 that are sequentially arranged from the side wall 21 side of the electrode through hole 20 to the center side of the electrode through hole 20. Will be described.

The adhesion layer 361 is a layer formed as necessary between other components of the through electrode 22 such as the seed layer 362 and the plating layer 363 and the side wall 21 of the through hole 20 for the electrode of the substrate 12. The adhesion layer 361 has higher adhesion to the substrate 12 than other components of the through electrode 22 such as the seed layer 362 and the plating layer 363. Further, the adhesion layer 361 suppresses the diffusion of metal elements in other components of the through electrode 22 such as the seed layer 362 and the plating layer 363 into the substrate 12 through the side wall 21 of the through hole 20 for the electrode. It may play the role of doing. When the seed layer 362 or the plating layer 363 contains copper, the material of the adhesion layer 361 is, for example, titanium, titanium nitride, molybdenum, molybdenum nitride, tantalum, tantalum nitride, or a laminate thereof. Can be done. Further, as the material of the adhesion layer 361, a conductive material having high adhesion to the substrate 12 may be used.

For example, as the material of the adhesion layer 361, titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, compounds thereof, alloys thereof, etc., or a laminated material thereof can be used. The thickness of the adhesion layer 361 is, for example, 10 nm or more and 1 μm or less. The adhesion layer 361 is formed by, for example, a physical film forming method such as a vapor deposition method or a sputtering method.

Further, the seed layer 362 has conductivity which serves as a base for growing the plating layer 363 by precipitating metal ions in the plating solution during the electrolytic plating step of forming the plating layer 363 by the electrolytic plating treatment. It is a layer. As the material of the seed layer 362, the same metal material as the plating layer 363, such as copper, can be used. The thickness of the seed layer 362 is, for example, 100 nm or more and 3 μm or less. The seed layer 362 is formed, for example, by electroless plating.

Although not shown, one layer that can serve as both an adhesion layer and a seed layer may be provided between the side wall 21 of the through hole 20 for the electrode and the plating layer 363. ..

Further, the plating layer 363 is a conductive layer formed by the plating treatment. As the material constituting the plating layer 363, metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel and chromium, alloys using these, or a laminated material thereof can be used. ..

Further, as shown in FIG. 2, the through electrodes 22 are formed on the adhesion layer 361 and the seed layer 362 formed along the side wall of the through hole 20 for the electrode, and the plating layer 363 formed on the surface of the seed layer 362. And have.

Here, as shown in FIG. 1, the through electrode substrate 10 may include an organic layer 26 located closer to the center of the through hole 20 for electrodes than the through electrode 22. The “center side” means that the distance between the organic layer 26 and the side wall 21 is larger than the distance between the through electrode 22 and the side wall 21 inside the through hole 20 for the electrode. The organic layer 26 contains an organic material having a dielectric loss tangent. As the organic material of the organic layer 26, polyimide, epoxy or the like can be used. By forming the organic layer 26 using an organic material having a small dielectric loss tangent, it is possible to prevent a part of the electric signal that should pass through the capacitor 15 and the inductor 16 from passing through the organic layer 26. As a result, the band of the through silicon via substrate 10 including the capacitor 15 and the inductor 16 can be expanded to the high frequency side.

(1st wiring structure part)
As shown in FIG. 1, the first wiring structure portion 30 is a first surface located on the first surface 13 of the substrate 12, the first surface first wiring layer 31, and the first surface located on the first surface first wiring layer 31. The second wiring layer 32 and the first surface third wiring layer 33 located on the first surface second wiring layer 32 are included. Hereinafter, the configurations of the first surface first wiring layer 31, the first surface second wiring layer 32, and the first surface third wiring layer 33 will be described.

[First surface, first wiring layer]
As shown in FIG. 1, the first surface first wiring layer 31 includes a first surface first conductive layer 311 including the first surface second electrode layer 15a of the capacitor 15, and a dielectric layer 15b of the capacitor 15. It has a first insulating layer 312 on one surface.

The first surface first conductive layer 311 is a conductive layer including the first wiring L1 and the first electrode portion 22a of the through silicon via 22 and located on the first surface 13 of the substrate 12.

The first surface first conductive layer 311 may be connected to the through electrode 22. Further, the first surface first conductive layer 311 may include an adhesion layer 361, a seed layer 362, and a plating layer 363 that are laminated in this order, similarly to the through electrode 22. The material constituting the first surface first conductive layer 311 is the same as the material constituting the through electrode 22. The thickness of the first surface first conductive layer 311 is, for example, 5 μm or more and 20 μm or less. In this case, as shown in FIG. 3, the capacitor 15 includes the adhesion layer 361 and the seed layer 362 formed on the inner surface of the through hole Z for the capacitor, and the plating layer 363 formed on the surface of the seed layer 362. Has.

Further, the first surface first insulating layer 312 is a layer having an insulating property, which is at least partially located on the first surface first conductive layer 311. The first surface first insulating layer 312 may partially cover the first surface first conductive layer 311. In this case, the first surface first insulating layer 312 may be in contact with not only the first surface first conductive layer 311 but also the first surface 13 of the substrate 12. Note that "covering" means, as shown in FIG. 3, when the through electrode substrate 10 is viewed along the normal direction of the first surface 13 of the substrate 12, the end portion 311e of the first surface first conductive layer 311 Means that the first surface and the first insulating layer 312 overlap at least partially.

Further, the first surface first insulating layer 312 contains an inorganic material having a dielectric breakdown electric field. As the inorganic material of the first surface first insulating layer 312, a silicon nitride such as SiN can be used. In addition, examples of the inorganic material of the first surface first insulating layer 312 include silicon oxide, aluminum oxide, and tantalum pentoxide. Thereby, the withstand voltage characteristic of the capacitor 15 including the first surface first insulating layer 312 functioning as the dielectric layer 15b can be further improved. The method for measuring the dielectric breakdown electric field will be described later in the examples. The relative permittivity of the inorganic material of the first surface first insulating layer 312 is, for example, 3 or more and 50 or less. The thickness of the first surface first insulating layer 312 is, for example, 50 nm or more and 400 nm or less.

[First side, second wiring layer]
As shown in FIG. 1, the first surface second wiring layer 32 has a first surface second conductive layer 321 and a first surface second insulating layer 322. The first surface second conductive layer 321 constituting the first surface first electrode layer 15c is a layer having conductivity located on the first surface first insulating layer 312. Then, as shown in FIGS. 1 and 3, the first surface first conductive layer 311 electrically connected to the through electrode 22, that is, the first surface second electrode layer 15a and the first surface first conductive layer 311 The first surface first insulating layer 312, that is, the dielectric layer 15b located above, and the first surface second conductive layer 321 located on the first surface first insulating layer 312, that is, the first surface first electrode layer 15c. The capacitor 15 is configured by the above.

As described above, the capacitor 15 is formed on the vicinity of the first surface opening Za of the first surface 13 of the through hole Z for the capacitor of the substrate 12, the side wall Za2 of the through hole Z for the capacitor, and the second surface 14 of the through hole Z for the capacitor. It has a laminated structure that is continuously provided over the vicinity of the second surface opening Zc and is laminated in the order of the first surface second electrode layer 15a, the dielectric layer 15b, and the first surface first electrode layer 15c.

It should be noted that a wiring layer (not shown) that electrically connects only one of the through electrode 22 and the first surface second electrode layer 15a or the first surface first electrode layer 15c of the capacitor 15 may be further provided. good.

Further, the first surface second conductive layer 321 is a close contact layer, a seed layer and a plating layer which are sequentially laminated on the first surface first insulating layer 312, similarly to the through electrode 22 and the first surface first conductive layer 311. May include. The material constituting the first surface second conductive layer 321 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 311. The thickness of the first surface second conductive layer 321 is, for example, 5 μm or more and 20 μm or less.

It should be noted that the first surface 13 side of the substrate 12 penetrates the first surface first electrode layer 15c and the dielectric layer 15b, is insulated from the first surface first electrode layer 15c, and is insulated from the first surface first electrode layer 15c. A through-hole wiring (not shown) electrically connected to the 15a may be further provided.

Further, as shown in FIG. 1, the first surface second insulating layer 322 is an insulating layer located on the first surface first insulating layer 312 and on the first surface second conductive layer 321. The first surface second insulating layer 322 contains an organic material having a dielectric loss tangent. As the organic material of the first surface second insulating layer 322, polyimide, epoxy or the like can be used. By forming the first surface second insulating layer 322 using an organic material having a small dielectric loss tangent, it is possible to prevent an electric signal that should pass through the capacitor 15 and the inductor 16 from passing through the first surface second insulating layer 322. be able to. As a result, the band of the through silicon via substrate 10 including the capacitor 15 and the inductor 16 can be expanded to the high frequency side.

Here, FIG. 5 is a diagram showing another example of the capacitor shown in FIG.

For example, as shown in FIG. 5, the first surface second electrode layer 15a, the dielectric layer 15b, and the first surface first electrode layer 15c of the adjacent capacitors 15 on the first surface 13 of the substrate 12 are the substrate 12 May be continuously connected on the first surface 13 of the above.

In the example of FIG. 5, the first surface second insulating layer 322 is formed in a part of the region surrounded by the first surface first electrode layer 15c inside the capacitor through hole Z. On the other hand, the first surface first electrode layer 15c and the first surface third conductive layer 331 above the first surface 13 adjacent to the through hole Z for the capacitor are electrically connected.
Further, FIG. 6 is a diagram showing still another example of the capacitor shown in FIG.

For example, as shown in FIG. 6, the first surface second electrode layer 15a, the dielectric layer 15b, and the first surface first electrode layer 15c of the capacitors 15 adjacent to each other on the first surface 13 of the substrate 12 are the substrate 12 It may not be continuously connected on the first surface 13 of the above.

For example, the first surface first electrode layer 15c and the first surface third conductive layer 331 of one capacitor 15 are electrically connected. The first surface first electrode layer 15c of the other two capacitors 15 is connected to a conductive layer (not shown). On the other hand, the first surface second electrode layer 15a of the three capacitors 15 is connected to a conductive layer (not shown).

In the example of FIG. 6, the inside of the through hole Z for the capacitor is embedded with the first surface second electrode layer 15a, the dielectric layer 15b, and the first surface first electrode layer 15c.

Here, FIG. 7 is a diagram showing an example of the configuration of the side end portion of the capacitor on the first surface of the through electrode substrate shown in FIG. 1.

For example, as shown in FIG. 7, the side end portion 15aY of the first surface second electrode layer 15a on the first surface 13 of the substrate 12 is covered with the dielectric layer 15b on the first surface 13. In the example of FIG. 7, the film thickness of the first surface second electrode layer 15a is, for example, 10 μm or more, which is thicker than the film thickness of the first surface first electrode layer 15c.

Further, as shown in FIG. 7, the side end portion 15bY of the dielectric layer 15b on the first surface 13 of the substrate 12 covers the end portion of the first surface second electrode layer 15a on the first surface 13 of the substrate 12. As such, it is located on the first surface 13 of the substrate 12.

Further, as shown in FIG. 7, the side end portion 15cY of the first surface first electrode layer 15c on the first surface 13 of the substrate 12 is the side end portion 15bY of the dielectric layer 15b on the first surface 13 of the substrate 12. It is located in the vicinity.

Further, as shown in FIG. 7, the first surface second electrode layer 15a has a recess 15aX at the boundary between the side end portion 15aY of the first surface second electrode layer 15a and the first surface 13 of the substrate 12. Then, the side end portion 15bY of the dielectric layer 15b and the side end portion 15cY of the first surface first electrode layer 15c are formed so as to fill the recess 15aX of the side end portion 15aY of the first surface second electrode layer 15a. ing.

As a result, the ratio of the area in contact between the dielectric layer 15b of the capacitor 15 and the first surface second electrode layer 15a and the first surface first electrode layer 15c can be increased to increase the capacity of the capacitor 15. ..

[First side, third wiring layer]
As shown in FIG. 1, the first surface third wiring layer 33 has a first surface third conductive layer 331 and a first surface third insulating layer 332. The first surface third conductive layer 331 is a layer having conductivity located on the first surface first conductive layer 311 or the first surface second conductive layer 321. In the example shown in FIG. 1, the first surface third conductive layer 331 is a portion connected to the first surface first conductive layer 311 which is one of the first surface second electrode layers 15a of the capacitor 15, and the capacitor 15 Includes a portion connected to the first surface second conductive layer 321 which is the other first surface first electrode layer 15c.

Further, the first surface third conductive layer 331 may include an adhesion layer, a seed layer, and a plating layer that are laminated in this order, similarly to the through electrode 22 and the first surface first conductive layer 311. The material constituting the first surface third conductive layer 331 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 311.

Further, the first surface third insulating layer 332 is a layer having an insulating property located on the first surface second insulating layer 322 and the first surface third conductive layer 331. The first surface third insulating layer 332, like the first surface second insulating layer 322, contains an organic material having a dielectric loss tangent. As the organic material of the first surface third insulating layer 332, polyimide, epoxy or the like can be used as in the case of the first surface second insulating layer 322.

(2nd wiring structure part)
As shown in FIG. 1, the second wiring structure portion 40 includes a second surface first wiring layer 41 located on the second surface 14 of the substrate 12. The second surface first wiring layer 41 has a second surface first conductive layer 411 and a second surface first insulating layer 412.

The second surface first conductive layer 411 is a conductive layer including the second wiring L2 and the second electrode portion 22b of the through electrode 22 and located on the second surface 14 of the substrate 12.

The second surface first conductive layer 411 may be connected to the through electrode 22. Further, the second surface first conductive layer 411 may include a close contact layer 361, a seed layer 362, and a plating layer 363 that are laminated in this order, similarly to the through electrode 22 and the first surface first conductive layer 311. The material constituting the second surface first conductive layer 411 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 311. The thickness of the first conductive layer 411 on the second surface is, for example, 5 μm or more and 20 μm or less.

Further, as shown in FIGS. 1 and 3, a second surface first conductive layer 411 located on the second surface 14 side, a through electrode 22 connected to the second surface first conductive layer 411, and a through electrode 22 The inductor 16 is formed by the first conductive layer 311 on the first surface, which is electrically connected to the first surface and is located on the 13th side of the first surface.

The second surface first insulating layer 412 is an insulating layer located on the second surface first conductive layer 411 and on the second surface 14 of the substrate 12. The second surface first insulating layer 412 contains an organic material having a dielectric loss tangent, like the first surface second insulating layer 322 and the first surface third insulating layer 332. As the organic material of the second surface first insulating layer 412, polyimide, epoxy or the like can be used as in the case of the first surface second insulating layer 322 and the first surface third insulating layer 332.

Manufacturing Method of Through Silicon Via Substrate An example of the manufacturing method of the through silicon via substrate 10 will be described below with reference to FIGS. 8 to 20.

(Through hole forming process)
First, the substrate 12 is prepared. Next, a resist layer is provided on the first surface 13. After that, an opening is provided in the resist layer at a position corresponding to the through hole 20 for the electrode and the through hole Z for the capacitor. Next, by processing the substrate 12 at the opening of the resist layer, as shown in FIG. 8, the through hole 20 for the electrode and the through hole Z for the capacitor can be formed in the substrate 12. As described above, the through hole 20 for the electrode penetrates the substrate 12, and the through hole Z for the capacitor penetrates the substrate 12, so that the etching conditions, the through hole 20 for the electrode, and the through hole Z for the capacitor Z Each aspect ratio, width, etc. of is set.

As a method for processing the substrate 12, a dry etching method such as a reactive ion etching method or a deep digging reactive ion etching method, a wet etching method, or the like can be used.

The electrode through hole 20 and the capacitor through hole Z may be formed in the substrate 12 by irradiating the substrate 12 with a laser. In this case, the resist layer may not be provided. As the laser for laser processing, an excimer laser, an Nd: YAG laser, a femtosecond laser, or the like can be used. When the Nd: YAG laser is adopted, a fundamental wave having a wavelength of 1064 nm, a second harmonic having a wavelength of 532 nm, a third harmonic having a wavelength of 355 nm, and the like can be used.

Further, laser irradiation and wet etching can be appropriately combined. Specifically, first, a alteration layer is formed in a region of the substrate 12 where the through hole 20 for an electrode and the through hole Z for a capacitor should be formed by laser irradiation. Subsequently, the substrate 12 is immersed in hydrogen fluoride or the like to etch the altered layer. As a result, the through hole 20 for the electrode and the through hole Z for the capacitor can be formed on the substrate 12.

In addition, the through hole 20 for the electrode and the through hole Z for the capacitor may be formed in the substrate 12 by a blast treatment of spraying an abrasive on the substrate 12.

In this way, the electrode through hole 20 including the first surface 13 and the second surface 14 located on the opposite side of the first surface 13 and penetrating between the first surface 13 and the second surface 14 A plurality of capacitor through holes Z that penetrate between the first surface 13 and the second surface 14 and have an opening Za and a second surface opening Zc of the second surface 14 are provided on the first surface 13. Prepare the substrate 12.

(Through Silicon Via Forming Process)
Next, the through electrode 22 is formed in the through hole 20 for the electrode, and the first surface second electrode layer 15a of the capacitor 15 is formed in the through hole Z for the capacitor. In the present embodiment, an example in which the above-mentioned first surface first conductive layer 311 and second surface first conductive layer 411 are formed at the same time as the through silicon via 22 will be described.

As shown in FIG. 9, a vapor deposition method, a sputtering method, or the like is performed on the first surface 13 and the second surface 14 of the substrate 12, the side wall 21 of the through hole 20 for the electrode, and the side wall Za2 of the through hole Z for the capacitor. The adhesion layer 361 is formed by a physical film forming method. Subsequently, a seed layer 362 is formed on the adhesion layer 361 by electroless plating. After that, the step of annealing the adhesion layer 361 and the seed layer 362 may be carried out.
The method of forming the adhesion layer 361 and the seed layer 362 is not limited to the above method. For example, the adhesion layer 361 containing zinc oxide or the like may be formed by the sol-gel method, and then the seed layer 362 may be formed on the adhesion layer 361 by the electroless plating method. Further, both the adhesion layer 361 and the seed layer 362 may be formed by a physical film forming method such as a vapor deposition method or a sputtering method.

Next, as shown in FIG. 10, a resist layer 37 is partially formed on the seed layer 362. Subsequently, as shown in FIG. 11, the plating layer 363 is formed on the seed layer 362 not covered by the resist layer 37 by electrolytic plating. Then, as shown in FIG. 12, the resist layer 37 is removed. Further, the portion of the adhesion layer 361 and the seed layer 362 covered by the resist layer 37 is removed by, for example, wet etching.

In this way, the first surface first conductive layer 311 and the second surface first conductive layer 411 including the through electrode 22 and the first surface second electrode layer 15a can be formed. As a result, the inductor 16 including the second surface first conductive layer 411, the through electrode 22 connected to the second surface first conductive layer 411, and the first surface first conductive layer 311 connected to the through electrode 22 Can be configured. The step of annealing the plating layer 363 may be carried out.

In particular, at the same time that the through electrode 22 is formed in the through hole 20 for the electrode, the first surface and the second electrode layer 15a of the capacitor 15 are formed in the through hole Z for the capacitor. More specifically, in the example of FIG. 12, the first surface and the second electrode layer 15a of the capacitor 15 are in the vicinity of the opening Za of the through hole Z for the capacitor of the substrate 12, the side wall Za2 of the through hole Z for the capacitor, and the through hole for the capacitor. It is formed so as to be continuous over the vicinity of the second surface opening Zc of the second surface 14 of Z.

(Surface treatment process)
Next, a surface treatment step of exposing the surface of the first surface first conductive layer 311 to _{plasma such as NH 3 plasma may be carried out.} Thereby, the oxide on the surface of the first conductive layer 311 on the first surface can be removed. For example, when the first surface first conductive layer 311 contains copper, the copper oxide on the surface of the first surface first conductive layer 311 can be removed. As a result, the adhesion between the first surface first conductive layer 311 and the first surface first insulating layer 312 formed on the first surface first conductive layer 311 can be enhanced.

(Step of forming the first insulating layer on the first surface)
Next, the first surface first insulating layer 312 including the dielectric layer 15b of the capacitor 15 is formed on the first surface first conductive layer 311.

First, as shown in FIG. 13, the resist layer 38 is partially formed on the first surface first conductive layer 311. Subsequently, as shown in FIG. 14, the first surface first surface 1 including the dielectric layer 15b in the portion of the first surface 1st conductive layer 311 and the first surface 13 of the substrate 12 that is not covered by the resist layer 38. The insulating layer 312 is formed. As a method for forming the first surface first insulating layer 312, for example, plasma CVD, sputtering, or the like can be adopted. Then, as shown in FIG. 15, the resist layer 38 is removed. In this way, the first surface first insulating layer 312 can be partially formed on the first surface first conductive layer 311 including the first surface second electrode layer 15a.

(Step of forming the first surface and the second conductive layer)
Next, as shown in FIG. 16, a first surface second conductive layer 321 including the first surface first electrode layer 15c is formed on the first surface first insulating layer 312 including the dielectric layer 15b. As a result, the first surface first conductive layer 311, the first surface first insulating layer 312 on the first surface first conductive layer 311 and the first surface second conductive layer on the first surface first insulating layer 312 321 and, that is, a capacitor 15 having a laminated structure in which the first surface second electrode layer 15a, the dielectric layer 15b, and the first surface first electrode layer 15c are laminated in this order can be configured.

Since the step of forming the first surface second conductive layer 321 is the same as the step of forming the first surface first conductive layer 311, the description thereof will be omitted.

In this way, along with the formation of the through electrodes 22, the capacitor 15 located on the first surface 13 side of the substrate 12 is formed.

(Step of forming the first surface and the second insulating layer)
Next, as shown in FIG. 17, the first surface second insulating layer 322 is formed on the first surface first insulating layer 312 and on the first surface second conductive layer 321. Further, the second surface first insulating layer 412 is formed on the second surface 14 of the substrate 12 and on the second surface first conductive layer 411.

For example, first, a second side film having a photosensitive layer containing an organic material and a base material is attached to the second side 14 side of the substrate 12. Subsequently, the second side film is subjected to an exposure treatment and a development treatment. As a result, the second surface first insulating layer 412 made of the photosensitive layer of the second surface side film can be formed on the second surface 14 side of the substrate 12.

Then, the first side film having the photosensitive layer containing the organic material and the base material is attached to the first side 13 side of the substrate 12. Subsequently, the first side film is exposed and developed so that the opening 323 shown in FIG. 18 is formed. As a result, the first surface first surface composed of the photosensitive layer of the first surface side film, in which the opening 323 is formed in a part on the first surface second conductive layer 321 and a part on the first surface first conductive layer 311. 2 Insulating layer 322 can be obtained.

By providing a part of the first surface second insulating layer 322 and a part of the second surface first insulating layer 412 inside the electrode through hole 20, an organic layer 26 for filling the electrode through hole 20 is formed. You may. For example, by pushing the above-mentioned second surface side film or first surface side film into the through hole 20 for the electrode, the electrode penetration is performed at the same time as the first surface second insulating layer 322 and the second surface first insulating layer 412. The organic layer 26 can be formed inside the hole 20. The organic layer 26 may be formed in a process different from that of the second surface first insulating layer 412 and the first surface second insulating layer 322.

The method of forming the second surface first insulating layer 412 and the first surface second insulating layer 322 is not limited to the method using a film. For example, first, a liquid containing an organic material such as polyimide is applied by a spin coating method or the like and dried to form an organic layer. Subsequently, the organic layer can be exposed and developed to form the second surface first insulating layer 412 and the first surface second insulating layer 322.

(Step of forming the first surface and the third conductive layer)
Next, as shown in FIG. 19, a portion of the first surface first insulating layer 312 that overlaps with the opening 323 of the first surface second insulating layer 322 is etched to open an opening in the first surface first insulating layer 312. Form.

Subsequently, the first surface is connected to the first surface first conductive layer 311 or the first surface second conductive layer 321 via the opening 323 of the first surface second insulating layer 322 and the opening of the first surface first insulating layer 312. The first surface third conductive layer 331 is formed. Since the step of forming the first surface third conductive layer 331 is the same as the step of forming the first surface first conductive layer 311, the description thereof will be omitted.

(Step of forming the first surface and third insulating layer)
After that, the first surface third insulating layer 332 is partially formed on the first surface second insulating layer 322 and on the first surface third conductive layer 331. As a result, the through silicon via substrate 10 shown in FIG. 1 can be obtained. The method for forming the first surface third insulating layer 332 is not particularly limited. As in the case of the first surface second insulating layer 322, the first surface third insulating layer 332 can be formed by using a film or liquid containing an organic material.

(Action of Through Silicon Via 10)
Hereinafter, the operation of the through silicon via substrate 10 according to the present embodiment will be described.

As described above, the substrate 12 is provided with an electrode through hole 20 extending from the first surface 13 to the second surface 14, that is, penetrating between the first surface 13 and the second surface 14. A plurality of through holes Z for capacitors are provided so as to penetrate between the first surface 13 and the second surface 14 and have an opening Za and a second surface opening Zc of the second surface 14 on the first surface 13.

A plurality of capacitors 15 are provided on the first surface 13 of the substrate 12 in a one-to-one correspondence with the through holes Z for each capacitor. In particular, the capacitor 15 is the vicinity of the first surface opening Za of the first surface 13 of the through hole Z for the capacitor of the substrate 12, the side wall Za2 of the through hole Z for the capacitor, and the second surface 14 of the second surface 14 of the through hole Z for the capacitor. It has a laminated structure that is continuously provided over the vicinity of the surface opening Zc and is laminated in the order of the first surface second electrode layer 15a, the dielectric layer 15b, and the first surface first electrode layer 15c.

As a result, the capacitor 15 can be mounted on the through electrode substrate 10 at a high density.

In the present embodiment, the substrate 12 of the through silicon via substrate 10 includes glass. Glass has higher insulating properties than silicon used as a substrate for a conventional through silicon via substrate. Therefore, it is possible to prevent a part of the high frequency signal passing through the capacitor 15 and the inductor 16 from passing through the substrate 12. As a result, the band of the capacitor 15 and the inductor 16 can be expanded to the high frequency side. Further, the withstand voltage characteristics of the capacitor 15 and the inductor 16 can be improved.

It is possible to make various changes to the above-described embodiment. Hereinafter, a modified example will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, the same codes as those used for the corresponding parts in the above-described embodiment will be used for the parts that can be configured in the same manner as in the above-described embodiment. Duplicate explanations will be omitted. Further, when it is clear that the action and effect obtained in the above-described embodiment can be obtained in the modified example, the description thereof may be omitted.

(First modification)
FIG. 20 is a cross-sectional view showing an example of a mounting substrate 60 including the through electrode substrate 10 shown in FIG. 1 and the element 50 mounted on the through electrode substrate 10. The element 50 is an LSI chip such as a logic IC or a memory IC. Further, the element 50 may be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic device in which machine element parts, sensors, actuators, electronic circuits, and the like are integrated on a single substrate. As shown in FIG. 20, the element 50 has a terminal 51 electrically connected to a conductive layer such as the first surface third conductive layer 331 of the through electrode substrate 10.

Although some modifications to the above-described embodiments have been described, it is naturally possible to apply a plurality of modifications in combination as appropriate.

Example of a Product on which a Through Silicon Via Substrate is Mounted FIG. 21 is a diagram showing an example of a product on which the through silicon via substrate 10 according to the embodiment of the present disclosure can be mounted. The through silicon via substrate 10 according to the embodiment of the present disclosure can be used in various products. For example, it is mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

10 Through electrode board 12 Board 13 First side 14 Second side 15 Capacitor 16 Inductor 20 Through hole for electrode Z Through hole for capacitor 50 Element 60 Mounting board 110 Notebook type personal computer 120 Tablet terminal 130 Mobile phone 140 Smartphone 150 Digital video camera 160 Digital camera 170 Digital clock 180 Server

Claims (15)

An electrode through hole that includes a first surface and a second surface located on the opposite side of the first surface and penetrates between the first surface and the second surface, and the first surface and the second surface. A substrate provided with a through hole for a capacitor that penetrates between the surfaces,
A through electrode located in the electrode through hole of the substrate and
Over the vicinity of the first surface opening of the first surface of the capacitor through hole of the substrate, the side wall of the capacitor through hole, and the vicinity of the second surface opening of the second surface of the capacitor through hole. provided continuously, the first face second electrode layer, a dielectric layer, Bei example a capacitor, a having a laminated structure are laminated in this order on the first surface the first electrode layer,
The side end portion of the first surface second electrode layer on the first surface of the substrate is covered with the dielectric layer on the first surface.
The side end portion of the dielectric layer on the first surface of the substrate is the first surface of the substrate so as to cover the end portion of the first surface second electrode layer on the first surface of the substrate. Located on the surface,
The side end portion of the first surface first electrode layer on the first surface of the substrate is located on the side end portion of the dielectric layer on the first surface of the substrate.
The first surface second electrode layer is a through electrode substrate having a recess at the boundary between the side end portion of the first surface second electrode layer and the first surface of the substrate. The through electrode substrate according to claim 1, further comprising a wiring layer for electrically connecting the through electrode and only one of the first surface second electrode layer and the first surface first electrode layer. The thickness of the first face second electrode layer, the greater thickness than the first surface first electrode layer, the through electrode substrate according to claim 1. The through electrode substrate according to claim 1, wherein the width of the through hole for the electrode is the same as the width of the through hole for the capacitor. The through electrode substrate according to claim 1, wherein the width of the through hole for the electrode is larger than the width of the through hole for the capacitor. On the first surface side of the substrate, the first surface first electrode layer and the dielectric layer are penetrated, and the first surface first electrode layer is insulated from the first surface first electrode layer, and the first surface second electrode layer is formed. The through electrode substrate according to claim 1, further comprising electrically connected through-hole wiring. The through electrode substrate according to claim 1, wherein the substrate is provided with a plurality of through holes for the capacitors, and the capacitors are provided in a one-to-one correspondence with the through holes for each capacitor. The first surface second electrode layer, the dielectric layer, and the first surface first electrode layer of the capacitor adjacent on the first surface of the substrate are continuous on the first surface of the substrate. 7. The through electrode substrate according to claim 7 , which is connected to the substrate. The first surface second electrode layer, the dielectric layer, and the first surface first electrode layer of the capacitor adjacent on the first surface of the substrate are continuous on the first surface of the substrate. The through electrode substrate according to claim 7 , which is not specifically connected. The through electrode substrate according to claim 1, wherein the cross section of the through hole for a capacitor parallel to the first surface is circular. The through electrode substrate according to claim 1, wherein the through electrode has a seed layer formed along the side wall of the through hole for the electrode and a plating layer formed on the surface of the seed layer. The through electrode, the first surface conductive layer electrically connected to the through electrode and located on the first surface side, and electrically connected to the through electrode and located on the second surface side. The through electrode substrate according to claim 1, further comprising an inductor having a second surface conductive layer. Through electrode substrate and
The element mounted on the through electrode substrate is provided.
The through electrode substrate is
An electrode through hole that includes a first surface and a second surface located on the opposite side of the first surface and penetrates between the first surface and the second surface, and the first surface and the second surface. A substrate provided with a through hole for a capacitor that penetrates between the surfaces,
A through electrode located in the electrode through hole of the substrate and
Over the vicinity of the first surface opening of the first surface of the capacitor through hole of the substrate, the side wall of the capacitor through hole, and the vicinity of the second surface opening of the second surface of the capacitor through hole. A capacitor having a laminated structure that is continuously provided and is laminated in the order of the first surface second electrode layer, the dielectric layer, and the first surface first electrode layer.
With
The side end portion of the first surface second electrode layer on the first surface of the substrate is covered with the dielectric layer on the first surface.
The side end portion of the dielectric layer on the first surface of the substrate is the first surface of the substrate so as to cover the end portion of the first surface second electrode layer on the first surface of the substrate. Located on the surface,
The side end portion of the first surface first electrode layer on the first surface of the substrate is located on the side end portion of the dielectric layer on the first surface of the substrate.
The first surface second electrode layer is a mounting substrate having a recess at the boundary between the side end portion of the first surface second electrode layer and the first surface of the substrate. An electrode through hole that includes a first surface and a second surface located on the opposite side of the first surface and penetrates between the first surface and the second surface, and the first surface and the second surface. The process of preparing a substrate provided with a through hole for a capacitor that penetrates between the surfaces, and
A step of forming a through electrode located in the through hole for the electrode of the substrate, and
Over the vicinity of the first surface opening of the first surface of the capacitor through hole of the substrate, the side wall of the capacitor through hole, and the vicinity of the second surface opening of the second surface of the capacitor through hole. A step of forming a capacitor having a laminated structure which is continuously provided and has a laminated structure in which a first surface second electrode layer, a dielectric layer, and a first surface first electrode layer are laminated in this order.
With
The side end portion of the first surface second electrode layer on the first surface of the substrate is covered with the dielectric layer on the first surface.
The side end portion of the dielectric layer on the first surface of the substrate is the first surface of the substrate so as to cover the end portion of the first surface second electrode layer on the first surface of the substrate. Located on the surface,
The side end portion of the first surface first electrode layer on the first surface of the substrate is located on the side end portion of the dielectric layer on the first surface of the substrate.
A method for manufacturing a through electrode substrate, wherein the first surface second electrode layer has a recess at a boundary between a side end portion of the first surface second electrode layer and the first surface of the substrate. The method for manufacturing a through electrode substrate according to claim 14 , wherein the through electrode is formed at the same time as the first surface and the second electrode layer of the capacitor are formed.

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