JP2011066331A - Mounting substrate and method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To downsize a mounting board in which an electrostatic capacitive element is built by limiting the size thereof. <P>SOLUTION: A through opening part (through-hole TH) is formed in resin substrates (10, 13 and 16), a lower electrode 20 is formed covering an internal wall of the through opening part of the resin substrates, a dielectric film 21 is formed as a layer on the lower electrode, an upper electrode 23 is formed as a layer on the dielectric film, and wiring (31, 32) is formed on the resin substrates. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a mounting substrate, a manufacturing method thereof, and an electronic device, and more particularly, to a mounting substrate incorporating a capacitive element, a manufacturing method thereof, and an electronic device.

Capacitance elements formed in a semiconductor integrated circuit device are required to be miniaturized and highly integrated in portable devices and the like simultaneously with high frequency and high speed. In addition, a single component that functions as a capacitance element (capacitor) is used together with a mounting substrate (printed wiring board) or the like separately from the semiconductor integrated circuit device. Since the capacitance value of such a single component capacitance element is much larger than the capacitance value of the capacitance element formed in the semiconductor integrated circuit device, the single component capacitance element is placed in the semiconductor integrated circuit device. It is practically impossible to replace the capacitor element.
Therefore, in recent years, development of a technique for taking a capacitive element into a mounting substrate has been advanced.

  For example, in the past, a single component capacitive element has been mounted on the surface of a mounting board. However, as described in Patent Document 1, a method of embedding a single component capacitive element in a mounting board is proposed. Has been.

  However, the embedding of such a single component capacitance element has a problem of limiting the thickness of the mounting substrate. Therefore, a technology for forming a next generation capacitor element directly on a mounting substrate has been attracting attention.

A conventional capacitive element structure of a mounting substrate having a capacitive element has a structure in which, for example, as described in Patent Document 2, two flat plate-like electrodes arranged in parallel and a dielectric film are disposed therebetween. Are known.
Conventionally, a dielectric sheet or the like has been used as the dielectric film, but the thickness of the sheet is several μm, and it has been difficult to ensure a large capacity.
On the other hand, in recent years, attention has been focused on applying a thin film forming technique such as sputtering as a method of forming a dielectric film.

The capacitance value of the capacitive element can be generally expressed as the following formula (1). C is a capacitance value, ε ₀ is a dielectric constant in vacuum, ε is a relative dielectric constant of a dielectric film to be used, S is an electrode area, and T is a film thickness of the dielectric film.

[Equation 1]
C = ε ₀ · ε · S / T (1)

  As is apparent from this equation, in the conventional capacitive element having the parallel plate type electrode formed on the mounting substrate, the capacitance value is proportional to the electrode area. Therefore, in order to form a large capacity element, a large occupied area is required.

JP 2003-152303 A JP 2008-78547 A JP 2008-34694 A

  The problem to be solved is that it is difficult to reduce the size of the mounting substrate by limiting the size of the mounting substrate in the conventional capacitive element structure built in the mounting substrate.

  The mounting substrate of the present invention includes a resin substrate having a through opening, a lower electrode formed so as to cover an inner wall of the through opening of the resin substrate, and a dielectric formed on an upper layer of the lower electrode. A body film; an upper electrode formed on an upper layer of the dielectric film; and a wiring formed on the resin substrate.

  In the mounting substrate of the present invention, a through opening is formed in a resin substrate, a lower electrode is formed so as to cover an inner wall of the through opening of the resin substrate, and a dielectric film is formed on an upper layer of the lower electrode. The upper electrode is formed on the upper layer of the dielectric film, and the wiring is formed on the resin substrate.

  The mounting substrate manufacturing method of the present invention includes a step of forming a through opening in a resin substrate, a step of forming a lower electrode so as to cover an inner wall of the through opening of the resin substrate, and an upper layer of the lower electrode Forming a dielectric film, forming an upper electrode on the dielectric film, and forming a wiring on the resin substrate.

  In the manufacturing method of the mounting substrate of the present invention, a through opening is formed in a resin substrate, a lower electrode is formed so as to cover an inner wall of the through opening of the resin substrate, and a dielectric film is formed on an upper layer of the lower electrode. The upper electrode is formed on the upper layer of the dielectric film, and the wiring is formed on the resin substrate.

  According to the mounting board of the present invention, the mounting board (printed wiring board) has a capacitive element, and the number of single-piece capacitive elements used can be reduced by replacing the single-piece capacitive element. This makes it possible to reduce mounting costs. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

  According to the method for manufacturing a mounting board of the present invention, a capacitive element can be formed in the mounting board (printed wiring board). As a result, by replacing with a single component capacitive element, the number of single component capacitive elements used can be reduced, and the mounting cost and the like can be reduced. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

FIG. 1A is a schematic cross-sectional view of a mounting substrate according to the first embodiment of the present invention, FIG. 1B is a plan view of a portion of a capacitive element, and FIG. It is the schematic cross section which expanded the part of the capacitive element. 2A to 2C are schematic cross-sectional views showing a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 3A and 3B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 4A and 4B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 5A and 5B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 6A and 6B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 7A and 7B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention. 8A and 8B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention. FIG. 9 is an enlarged schematic cross-sectional view of a capacitive element portion of a mounting board according to the third embodiment of the present invention.

  Embodiments of a mounting substrate and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

The description will be given in the following order.
1. First embodiment (overall configuration)
2. Second embodiment (manufacturing method by lift-off)
3. Third embodiment (a method of batch processing from the upper electrode to the lower electrode)
4). Fourth Embodiment (Method of forming by ALD method from upper electrode to lower electrode)

<First Embodiment>
[Configuration of entire mounting board]
FIG. 1A is a schematic cross-sectional view of a mounting substrate according to the present embodiment.
The resin substrate 1 is configured by, for example, laminating a plurality of resin layers, the internal wiring 2 and the inter-wiring contact 3 are embedded therein, the surface wiring 4 is formed on the surface, and the mounting substrate is It is configured.
For example, as shown in FIG. 1A, the mounting substrate of the present embodiment is used by mounting the semiconductor chip 5 on a flip chip via bumps. Alternatively, other electronic elements can be mounted. It can also be mounted by a method other than flip chip.
Here, the capacitive element 6 is formed on the mounting substrate according to the present embodiment.

[Configuration of capacitance element]
FIG. 1B is an enlarged plan view of a portion of the capacitive element 6 formed on the mounting substrate according to the present embodiment, and FIG. 1C is a schematic cross-sectional view.
For example, the first conductive layer 11 is patterned on one surface of the first resin layer 10, and the second conductive layer 12 is patterned on the other surface.
The third conductive layer 14 is patterned on one surface of the second resin layer 13, and the fourth conductive layer 15 is patterned on the other surface.
The first resin layer 10 and the second resin layer 13 having the above-described configuration are laminated via the third resin layer 16 from the second conductive layer 12 and the fourth conductive layer 15 side, respectively, and serve as a core (hereinafter referred to as a core). Substrate CS) is formed.
For example, the 1st resin layer 10, the 2nd resin layer 13, and the 3rd resin layer 16 consist of prepregs, respectively. The first conductive layer 11, the second conductive layer 12, the third conductive layer 14, and the fourth conductive layer 15 are formed by patterning a conductor such as a copper foil.

A through-hole (through opening) TH that penetrates the core substrate CS having the above-described configuration is formed.
For example, the lower electrode 20 is formed so as to cover the inner wall of the through hole TH and a nearby region, the dielectric film 21 is formed on the upper layer of the lower electrode 20, and the upper electrode is formed on the upper layer of the dielectric film 21. 23 is formed. That is, in the through hole TH, the lower electrode 20, the dielectric film 21, and the upper electrode 23 are stacked in a cylindrical shape.

In a region in the vicinity of the through hole TH that is outside the through hole TH, the lower electrode 20, the dielectric film 21, and the upper electrode 23 have the following configuration.
As shown in FIGS. 1B and 1C, for example, the lower electrode 20 is formed wider than the upper electrode 23. That is, the formation region of the lower electrode 20 protrudes from the formation region of the upper electrode 23.
Further, for example, the dielectric film 21 is formed narrower than the lower electrode 20 and wider than the upper electrode 23. That is, the formation region of the dielectric film 21 protrudes from the formation region of the upper electrode 23, and the formation region of the lower electrode 20 protrudes from the formation region of the dielectric film 21.

The lower electrode 20 is a film formed by directly depositing a conductor so as to cover the inner wall of the through hole TH and a nearby region.
The dielectric film 21 is a film formed by directly depositing a dielectric so as to cover the surface of the lower electrode 20.
The upper electrode 23 is a film formed by directly depositing a conductor so as to cover the surface of the dielectric film 21.
With the above-described configuration, a capacitive element in which the lower electrode 20, the dielectric film 21, and the upper electrode 23 are laminated is configured.
The lower electrode 20 is formed to be connected to the first conductive layer 11 and the third conductive layer 14, and the lower electrode is constituted by the lower electrode 20, the first conductive layer 11 and the third conductive layer 14. it can. Thereby, the parasitic resistance of the lower electrode 20 can be reduced, and a capacitance element suitable for high-frequency circuit applications can be obtained.

  The dielectric film 21 is a film formed by, for example, an atomic layer deposition (ALD) method. The dielectric film 21 is made of, for example, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, or a stacked or mixed material of these materials. Alternatively, a material obtained by adding another element to the above material is used.

  The lower electrode 20 and the upper electrode 23 are, for example, films formed by an atomic layer deposition method, respectively. The lower electrode 20 and the upper electrode 23 are made of, for example, a metal material such as Ru, Mo, or Pt, or a nitride of a metal element contained in the dielectric material of the dielectric film 21, such as hafnium nitride, zirconium nitride, or tantalum nitride. Conductive nitrides such as titanium nitride are used. In the case of conductive nitride, it is possible to prevent oxygen in the dielectric film from diffusing into the first conductive layer 11 or the third conductive layer 14.

  Further, for example, the fourth resin layer 30 is formed in the region inside the upper electrode 23 in the through hole HT and the upper and lower surfaces of the core substrate CS. That is, the fourth resin layer 30 is laminated on both surfaces of the core substrate CS formed by laminating the first resin layer 10, the second resin layer 13, and the third resin layer 16, and the resin substrate 1 shown in FIG. The resin substrate RS formed by laminating resin layers is configured.

Further, a fifth conductive layer 31 and a sixth conductive layer 32 are laminated and patterned on one surface of the fourth resin layer 30, and the resin substrate RS corresponding to the surface wiring 4 shown in FIG. It becomes the wiring of the surface. Further, a fifth conductive layer 31 is patterned on the other surface of the fourth resin layer 30 and becomes a wiring on the surface of the resin substrate RS corresponding to the surface wiring 4 shown in FIG.
On the other hand, the 1st conductive layer 11, the 2nd conductive layer 12, the 3rd conductive layer 14, and the 4th conductive layer 15 comprise the wiring inside resin board RS equivalent to internal wiring 2 shown in Drawing 1 (a). .

Further, for example, an opening CT1 reaching the upper electrode 23 is formed in the fifth conductive layer 31 and the fourth resin layer 30, and an extraction electrode 33 connected to the upper electrode 23 is formed.
Further, for example, an opening CT2 reaching the lower electrode 20 is formed in the fifth conductive layer 31 and the fourth resin layer 30, and an extraction electrode 34 connected to the lower electrode 20 is formed.

  As described above, in the portion on the inner wall surface of the through hole TH and the upper layer of the fourth resin layer 30 outside the through hole TH, the lower electrode 20 and the upper electrode 23 face each other with the dielectric film 21 interposed therebetween. The capacitive element of the mounting substrate according to the embodiment is configured.

The capacitance value of the capacitive element formed on the mounting substrate of the present embodiment is determined through the dielectric film 21 between the portion of the inner wall surface of the through hole TH and the upper layer of the fourth resin layer 30 outside the through hole TH. Depending on the area where the lower electrode 20 and the upper electrode 23 face each other.
On the inner wall surface of the through hole, a large area can be ensured as an area where the lower electrode 20 and the upper electrode 23 face each other as compared with the conventional capacitance element. As a result, the effective electrode area can be increased with respect to the occupied area of the capacitive element, and a large-capacity element can be obtained with a small occupied area.

[Method of forming electrostatic capacitance element]
2 to 6 are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the present embodiment.
First, as shown in FIG. 2A, for example, the first conductive layer 11 and the second conductive layer 12 are formed on both surfaces of the first resin layer 10 made of prepreg. The first conductive layer 11 and the second conductive layer 12 are conductors such as a copper foil bonded to the first resin layer 10.

  Next, as shown in FIG. 2B, for example, a dry film having a desired region opened on the first conductive layer 11 and the second conductive layer 12 is patterned to form the first conductive layer 11 and the first conductive layer 11. The pattern of the two conductive layers 12 is etched. Although the drawing shows that only the second conductive layer 12 is etched, the first conductive layer 11 may be processed into a desired pattern in a region outside the drawing.

Next, as shown in FIG. 2C, the third conductive layer 14 and the fourth conductive layer 15 are pattern-formed on both surfaces of the second resin layer 13 made of prepreg in the same manner as described above.
Furthermore, the 3rd resin layer 16 for bonding which consists of prepregs is prepared.

  Next, as shown in FIG. 3A, the first resin layer 10 and the second resin layer 13 having the above-described configuration are connected to the third resin layer 16 from the second conductive layer 12 and the fourth conductive layer 15 side, respectively. The core substrate CS is formed by stacking and pressing.

  Next, as shown in FIG. 3B, through holes TH are formed in the core substrate CS using, for example, a drill.

  Next, as shown in FIG. 4A, for example, a conductor is directly deposited on the entire surface including the side wall of the through-hole TH by an electroless plating method using a palladium catalyst or the like to form the lower electrode 20. A conductive layer is formed. This step can also be used as a step of forming an existing through via wiring.

  The lower electrode 20 is formed to be connected to the first conductive layer 11 and the third conductive layer 14, and the lower electrode is constituted by the lower electrode 20, the first conductive layer 11 and the third conductive layer 14. it can. Thereby, the parasitic resistance of the lower electrode 20 can be reduced, and a capacitance element suitable for high-frequency circuit applications can be formed.

  Next, as shown in FIG. 4B, for example, a dielectric film 21 is formed by directly depositing a dielectric so as to cover the surface of the lower electrode 20.

As a method of forming the dielectric film 21, for example, it is preferable to form the dielectric film 21 by low-temperature film formation in which the resin substrate is formed at a temperature lower than the temperature at which the resin substrate is damaged. Here, the heat resistant temperature of the resin substrate is, for example, 150 ° C., and the temperature for low-temperature film formation is about 100 to 130 ° C.
As a method for realizing low-temperature film formation, for example, a plasma ALD method in which oxidation or nitridation is performed by a plasma reaction using oxygen or ozone as an oxidation source, nitrogen or ammonia as a nitridation source, and the like can be used. In the case of an oxide film, a thermal ALD method using hydrolysis in which a reaction between an organic material containing silicon or metal and H ₂ O proceeds even at a low temperature can be used.
Alternatively, the dielectric film is formed by using a low temperature plasma CVD (Chemical Vapor Deposition) method using a high density plasma source such as ECR (Electron Cyclotron Resonance) or a low temperature thermal CVD method using hydrolysis. May be performed.

  For example, it is preferable to use an ALD method with good step coverage. Examples of the dielectric material constituting the dielectric film 21 include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, and these materials. A material obtained by stacking or mixing these materials, or a material obtained by adding another element to the above materials can be used.

Next, as shown in FIG. 5A, the dry film 22 is patterned so as to open the area of the capacitive element.
Next, an upper electrode 23 is formed by directly depositing a conductor so as to cover the surface of the dielectric film 21 by an electroless plating method using a palladium catalyst or the like.

In forming the lower electrode 20 and the upper electrode 23, it is preferable to use an ALD method with good step coverage in addition to the electroless plating method.
For example, the lower electrode 20, the dielectric film 21, and the upper electrode 23 can be continuously formed by the ALD method.
As the conductive material, a conductive material such as a metal material such as Ru, Mo, Pt, or a nitride of a metal element contained in the dielectric material of the dielectric film 21, such as hafnium nitride, zirconium nitride, tantalum nitride, or titanium nitride. A reactive nitride material is used. This is effective in preventing oxygen in the dielectric film from diffusing into the first conductive layer 11 or the third conductive layer 14.
By the above ALD method, the lower electrode 20, the dielectric film 21, and the upper electrode 23 can be continuously formed.

Next, as shown in FIG. 5B, for example, the upper film 23 is patterned by lift-off by removing the dry film 22 described above.
Next, the dry film 24 is patterned so as to open a desired region in the upper layer of the upper electrode 23. Here, the dielectric film 21 is formed so as to protect the formation region.
Next, an etching process such as wet etching or dry etching is performed using the dry film 24 as a mask to pattern the dielectric film 21.

Next, as shown in FIG. 6A, for example, the dry film 24 is removed, and the dry film 25 is patterned so that a desired region is opened in the upper layer of the upper electrode 23 and the dielectric film 21. To do. Here, it is formed so as to protect the formation region of the lower electrode 20.
Next, an etching process such as dry etching is performed using the dry film 25 as a mask to pattern the lower electrode 20 and the first conductive layer 11.
In the above process, the conductive layer to be the first conductive layer 11 and the lower electrode 20 in a region outside the drawing may be processed into a desired pattern to form an internal wiring.

Next, the dry film 25 is removed, and, as shown in FIG. 6B, for example, the fourth resin layer 30 is formed on the entire surface of the core substrate CS so as to cover the area of the capacitive element. A fifth conductive layer 31 is formed on the upper layer. For example, the fourth resin layer 30 on which the fifth conductive layer 31 is formed can be formed by bonding the both sides of the core substrate CS to each other by pressing.
By the above pressing, the fourth resin layer 30 is formed so as to be embedded in the region inside the upper electrode 23 in the through hole TH.

Next, for example, the opening CT <b> 1 reaching the upper electrode 23 is formed in the fifth conductive layer 31 and the fourth resin layer 30. For example, a dry film having a contact region with respect to the upper electrode 23 is patterned, the fifth conductive layer 31 is patterned and opened, and then the fourth resin layer 30 is opened by, for example, laser processing. To do.
Similarly to the above, an opening CT2 reaching the lower electrode 20 is formed in the fifth conductive layer 31 and the fourth resin layer 30. For example, a dry film having a contact region with respect to the lower electrode is patterned, the fifth conductive layer 31 is opened by pattern etching, and then the fourth resin layer 30 is opened by, for example, laser processing. .

Next, for example, a conductive layer is formed by embedding the inside of the opening CT1 by an electroless plating method using a palladium catalyst or the like, and an extraction electrode 33 connected to the upper electrode 23 is formed.
At the same time as described above, for example, a conductive layer is formed by filling the opening CT <b> 2, and the extraction electrode 34 connected to the lower electrode 20 is formed.

The capacitance value of the capacitive element formed by the mounting substrate manufacturing method of the present embodiment is a dielectric film between the portion on the inner wall surface of the through hole TH and the upper layer of the fourth resin layer 30 outside the through hole TH. 21, depending on the area where the lower electrode 20 and the upper electrode 23 face each other.
On the inner wall surface of the through hole, a large area can be ensured as an area where the lower electrode 20 and the upper electrode 23 face each other as compared with the conventional capacitance element. As a result, the effective electrode area can be increased with respect to the occupied area of the capacitive element, and a large-capacity element can be formed in a small occupied area.

  In the mounting substrate manufacturing method of the present embodiment, the number of resin layers constituting the resin substrate is not limited. Even if a plurality of resin layers are laminated, it is possible to easily open through with a drill or the like, and a larger capacity value can be obtained as the number of layers increases.

Second Embodiment
[Method of forming electrostatic capacitance element]
The capacitive element of the mounting board according to the present embodiment is substantially the same as that of the first embodiment.
The mounting substrate manufacturing method according to this embodiment is performed in the same manner as in the first embodiment up to the step shown in FIG. 4A of the first embodiment.
Next, as shown in FIG. 7A, the dry film 26 is patterned so as to open the region of the capacitance element.
Next, the dielectric film 21 is formed by directly depositing a dielectric so as to cover the surfaces of the lower electrode 20 and the dry film 26 by an ALD method with good step coverage.

  Next, as shown in FIG. 7B, for example, by removing the dry film 26, the dielectric film 21 is patterned by lift-off.

Next, as shown in FIG. 8A, the dry film 27 is patterned so as to open the area of the capacitive element.
Next, a conductor is directly deposited so as to cover the surfaces of the dielectric film 21 and the dry film 27 by using an electroless plating method using a palladium catalyst or an ALD method with good step coverage to form the upper electrode 23. To do.

Next, as shown in FIG. 8B, for example, the upper film 23 is patterned by lift-off by removing the dry film 27 described above.
The subsequent steps can be performed in the same manner as in the first embodiment.
By adopting such a manufacturing method, it is possible to avoid damage to the lower electrode, which is a base, and a reduction in film thickness due to over-etching when the dielectric film 21 is processed.

The capacitance value of the capacitive element formed by the mounting substrate manufacturing method of the present embodiment is a dielectric film between the portion on the inner wall surface of the through hole TH and the upper layer of the fourth resin layer 30 outside the through hole TH. 21, depending on the area where the lower electrode 20 and the upper electrode 23 face each other.
On the inner wall surface of the through-hole TH, a larger area can be secured as an area where the lower electrode 20 and the upper electrode 23 face each other as compared with a conventional electrostatic capacitance element. As a result, the effective electrode area can be increased with respect to the occupied area of the capacitive element, and a large-capacity element can be obtained with a small occupied area.

<Third Embodiment>
[Configuration and Forming Method of Capacitance Element]
In the mounting substrate manufacturing method according to the first embodiment and the second embodiment, the dielectric film 21 is processed by etching or lift-off for pattern processing of the dielectric film 21, but this process is not necessarily performed. Not necessary.
FIG. 9 is an enlarged schematic cross-sectional view of the capacitive element portion of the mounting board according to the present embodiment.

After the dielectric film 21 is formed on the entire surface of the lower electrode 20, patterning of the lower electrode 20 is performed using a dry film or the like for patterning the lower electrode 20 without patterning only the dielectric film 21. At the same time, patterning of the dielectric film 21 is performed. This is because the dielectric film 21 and the lower electrode 20 can be patterned continuously by changing the conditions such as etching using the dry film as a mask.
Thereafter, when forming the opening CT2 for the lower electrode 20, the opening CT2 can be formed by removing the dielectric film 21.
According to said manufacturing method, the patterning process process which processes a dielectric film can be abbreviate | omitted, the number of processes can be reduced, and cost reduction is implement | achieved.

The capacitance value of the capacitive element formed by the mounting substrate manufacturing method of the present embodiment is a dielectric film between the portion on the inner wall surface of the through hole TH and the upper layer of the fourth resin layer 30 outside the through hole TH. 21, depending on the area where the lower electrode 20 and the upper electrode 23 face each other.
On the inner wall surface of the through-hole TH, a larger area can be secured as an area where the lower electrode 20 and the upper electrode 23 face each other as compared with a conventional electrostatic capacitance element. As a result, the effective electrode area can be increased with respect to the occupied area of the capacitive element, and a large-capacity element can be formed in a small occupied area.

<Fourth embodiment>
In the present embodiment, all or part of the lower electrode in the through hole TH is formed by the ALD method. As a result, fine irregularities on the surface of the lower electrode are alleviated, and the reliability of the capacitive element is improved.
Alternatively, all or part of the upper electrode is formed by the ALD method. This makes it possible to form an electrode with excellent coverage.
The electrode material formed by the ALD method includes TiN and the like, but is preferably formed of a conductive nitride obtained by nitriding a metal element contained in the dielectric film 21.
Of course, all or part of the lower electrode 20 and the upper electrode 23 can be formed by the ALD method. By forming continuously with the dielectric film 21, a clean interface can be obtained, and the occurrence of leakage current due to traps and the like can be suppressed, and high reliability can be obtained.
Except for the above, it can be formed in the same manner as the manufacturing method of the mounting substrate of the first to third embodiments.

The capacitance value of the capacitive element formed by the mounting substrate manufacturing method of the present embodiment is a dielectric film between the portion on the inner wall surface of the through hole TH and the upper layer of the fourth resin layer 30 outside the through hole TH. 21, depending on the area where the lower electrode 20 and the upper electrode 23 face each other.
On the inner wall surface of the through-hole TH, a larger area can be secured as an area where the lower electrode 20 and the upper electrode 23 face each other as compared with a conventional electrostatic capacitance element. As a result, the effective electrode area can be increased with respect to the occupied area of the capacitive element, and a large-capacity element can be formed in a small occupied area.

The present invention is not limited to the above description.
For example, in the above-described embodiment, after laminating three resin layers and four conductive layers, the through hole TH to be a capacitive element is formed to form the capacitive element, but the present invention proposes. The capacitive element structure is not limited to this. For example, it is also possible to form a through-hole TH after laminating four or more resin layers and six or more conductive layers, thereby forming a capacitive element. It is also possible to form a through-hole TH after laminating one or two resin layers and two conductive layers to form a capacitive element.
The through-hole TH is not limited to a cylindrical shape, and an effect can be obtained even in a shape such as a square or a triangle. The larger the area of the wall surface per unit area as viewed from above, the more preferable.
Furthermore, in the above embodiment, one through hole TH is used for one capacitive element. However, an upper electrode and a lower electrode are formed so as to be connected to a plurality of through holes TH, thereby forming one capacitive element. Thus, it is possible to efficiently form a larger capacitance value.
Further, the present invention can be applied to an electronic device in which a semiconductor chip or various electronic components are mounted on the mounting board.
In addition, various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Resin substrate, 2 ... Internal wiring, 3 ... Contact between wiring, 4 ... Surface wiring, 5 ... Semiconductor chip, 6 ... Electrostatic capacitance element, 10 ... 1st resin layer, 11 ... 1st conductive layer, 12 ... 1st 2 conductive layers, 13 ... 2nd resin layer, 14 ... 3rd conductive layer, 15 ... 4th conductive layer, 16 ... 3rd resin layer, 20 ... lower electrode, 21 ... dielectric material film, 22, 24, 25, 26 , 27 ... dry film, 23 ... upper electrode, 30 ... fourth resin layer, 31 ... fifth conductive layer, 32 ... sixth conductive layer, 33, 34 ... take-out electrode, CT1, CT2 ... opening, TH ... through hole

Claims (15)

A resin substrate having a through opening formed thereon;
A lower electrode formed to cover at least the inner wall of the through-opening of the resin substrate;
A dielectric film formed on an upper layer of the lower electrode;
An upper electrode formed in an upper layer of the dielectric film;
And a wiring board formed on the resin substrate. A resin layer is formed on the inner region of the upper electrode in the through-opening and on the upper and lower surfaces of the resin substrate,
The mounting board according to claim 1, wherein the wiring is formed on the resin layer. An opening reaching the lower electrode and an opening reaching the upper electrode are formed in the resin layer,
The mounting substrate according to claim 2, wherein extraction electrodes connected to the lower electrode and the upper electrode are respectively formed in the opening reaching the lower electrode and the opening reaching the upper electrode. The mounting substrate according to claim 1, wherein the dielectric film is a film formed by directly depositing on an upper layer of the lower electrode. The mounting substrate according to claim 4, wherein the dielectric film is a film formed by atomic layer deposition. The lower electrode is a film formed by directly depositing so as to cover the inner wall and the vicinity of the through opening of the resin substrate,
The mounting substrate according to claim 4, wherein the upper electrode is a film formed by being directly deposited on an upper layer of the dielectric film. The mounting substrate according to claim 6, wherein each of the lower electrode and the upper electrode is a film formed by atomic layer deposition. Forming a through opening in the resin substrate;
Forming a lower electrode so as to cover at least an inner wall of the through opening of the resin substrate;
Forming a dielectric film on the upper layer of the lower electrode;
Forming an upper electrode on an upper layer of the dielectric film;
Forming a wiring on the resin substrate. Further comprising a step of forming a resin layer on the inner region of the upper electrode in the through-opening and on the upper and lower surfaces of the resin substrate;
The method for manufacturing a mounting substrate according to claim 8, wherein in the step of forming the wiring, the wiring is formed on the resin layer. After the step of forming the resin layer,
Forming an opening reaching the lower electrode and an opening reaching the upper electrode in the resin layer, and
The method of manufacturing a mounting substrate according to claim 9, further comprising: forming an extraction electrode connected to each of the lower electrode and the upper electrode in an opening reaching the lower electrode and an opening reaching the upper electrode. The method for manufacturing a mounting substrate according to claim 8, wherein in the step of forming the dielectric film, the dielectric film is directly deposited on an upper layer of the lower electrode. The method for manufacturing a mounting substrate according to claim 11, wherein the dielectric film is formed by atomic layer deposition in the step of forming the dielectric film. In the step of forming the lower electrode, a conductor is directly deposited so as to cover the inner wall and the vicinity of the through opening of the resin substrate,
The method for manufacturing a mounting substrate according to claim 11, wherein in the step of forming the upper electrode, a conductor is directly deposited on an upper layer of the dielectric film. The method for manufacturing a mounting substrate according to claim 13, wherein the formation is performed by atomic layer deposition in the step of forming the lower electrode and the step of forming the upper electrode.   The electronic device carrying the mounting substrate of Claim 1-14.

Images