JP2011082301A - Wiring board, method of manufacturing the same, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacity element built-in type wiring board large in capacity value, small in occupation area, relatively low in height and free from terminal connection failure. <P>SOLUTION: A capacitor CAP is embedded in a board resin layer 6 in a wiring board. The capacitor CAP includes a first capacitive electrode 2, a dielectric film 3 and a second capacitive electrode 4. The first capacitive electrode 2 has a surface shaped with successive protruded steps such as protruded step members 23 or the like. The dielectric film 3 covers the surface and an electrode material of a reinforcing electrode member 42 (a part of the second capacitive electrode 4) with the dielectric film interposed between the protruded steps on the surface is filled. The reinforcing electrode member 42 also serves as a reinforcing member of maintaining and reinforcing the surface shape of the protruded steps. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a wiring board in which a capacitive element is embedded in a substrate resin layer, a method for manufacturing the wiring board, and an electronic device incorporating the wiring board.

  Capacitance elements formed in a semiconductor integrated circuit are required to be miniaturized and highly integrated in portable devices and the like simultaneously with high frequency and high speed. In addition, in a printed wiring board or the like, a single component that functions as a capacitor is used together with a semiconductor integrated circuit. Since the capacitance value of such a single component capacitor is much larger than the capacitance value of a capacitive element (capacitor) formed in a semiconductor integrated circuit, it is not possible to replace a single component capacitor with a capacitive element in a semiconductor integrated circuit. Not easy.

  A large-capacity capacitor that is a single component mounted on the surface of a wiring board hinders the thickness reduction of electronic devices. For this reason, in recent years, technological development for taking in a relatively large capacitive element into a wiring board has been advanced. For example, a method of embedding a single component capacitor in a wiring board has been proposed (see, for example, Patent Document 1).

  Also, a technique is known in which two flat plate-like electrodes arranged in parallel inside a wiring board and a capacitor element in which a dielectric film is arranged between them are formed (see, for example, Patent Document 2).

  If a capacitive element can be formed in the wiring board as in Patent Document 2, it can be replaced with a single component capacitor, the number of single component capacitors used can be reduced, and the mounting cost and the like can be reduced.

Further, when embedding a single component capacitor in a wiring board, a certain amount of height is required, so that a space, particularly a height direction space, is required across a plurality of layers of the multilayer wiring board.
On the other hand, since the parallel plate type capacitive element can be reduced in height (thickness), it can be formed in one layer of a multilayer wiring substrate (a portion where two wiring layers are sandwiched between substrate resin layers).

JP 2003-152303 A JP 2008-78547 A

  Patent Document 1 discloses an embodiment in which a single component capacitor is embedded in a through hole of a (printed) wiring board.

  However, if a comparatively large through hole is formed in advance in such a wiring board, the rigidity of the wiring board is lowered. Although Patent Document 1 describes that after mounting a single component capacitor in a through hole, the gap is filled (with a filler), the rigidity of the wiring board may still be insufficient.

Moreover, workability when mounting a single component capacitor and electrically connecting the wiring layer and the capacitor at the bottom of a deep hole is poor.
In Patent Document 1, the gap around the capacitor is embedded (with a filler). However, if the gap is not sufficiently filled, there is a concern that reliability may be lowered due to the entry of the processing liquid or the like.

  Patent Document 1 also exemplifies an embodiment in which a single component capacitor is embedded in a substrate and an embodiment in which the capacitor is mounted on a side surface of the substrate.

However, when embedding the capacitor inside the substrate, the capacitor is electrically and mechanically connected to the conductor layer, and then the resin is filled around the capacitor to complete the wiring substrate. For this reason, there is a concern that the terminal connection failure of the capacitor may occur due to the stress when the resin having high fluidity is filled or the external force after completion.
This connection terminal failure may occur regardless of surface mounting or internal mounting as long as a single component capacitor is separately made and mounted on the wiring board later.

  Further, as described above, embedding the single component capacitor has a disadvantage that it limits the thickness of the wiring board.

  On the other hand, when the parallel plate type capacitive element is embedded in the wiring board as in Patent Document 2 described above, this formation is possible even if the wiring board is thin.

  When the capacitive element is formed integrally with the wiring board instead of a single component as in Patent Document 2, a via hole for drawing out an element electrode is usually formed by laser irradiation after filling the resin. Therefore, there is no concern that the terminal connection failure of the capacitive element occurs due to the stress through the resin or the like.

  However, in Patent Document 2, when a high capacitance value is realized, the area occupied by the parallel plate type capacitive element is increased. Therefore, when many elements including capacitive elements are arranged in the wiring board, the arrangement space is limited. Therefore, when a large capacitive element is to be arranged, there is a disadvantage that the size (area) of the wiring board increases.

  As described above, the capacitive element embedded in the wiring board has a small occupied area in the case of a single component, but is high, whereas in the parallel plate type, the occupied area is increased in a small height. In addition, there is a concern of poor terminal connection in the case of a single component, and there is a disadvantage that the capacity value cannot be increased in the case of a parallel plate type.

  The present invention provides a wiring board with a built-in capacitive element that has a small occupation area and a relatively small height even when a large capacitance value is set, and that has no fear of terminal connection failure and high reliability. Moreover, this invention provides the manufacturing method of the said wiring board.

In the wiring substrate according to the present invention, a capacitive element is embedded in one of the substrate resin layers inside the substrate in which a plurality of wiring layers are laminated with a substrate resin layer interposed between layers. The capacitive element includes a first capacitive electrode, a dielectric film, and a second capacitive electrode.
The first capacitor electrode is supported by one wiring layer and has a surface in which a plurality of convex steps are continuous.
The dielectric film covers the surface of the first capacitor electrode.
The second capacitor electrode is filled with the dielectric film interposed between convex steps on the surface of the first capacitor electrode. Accordingly, the second capacitor electrode also serves as a reinforcing member that maintains and reinforces the surface shape of the convex step.

  According to this configuration, the capacitance value of the capacitive element is determined by the total area of the portion where the first capacitive electrode and the second capacitive electrode face each other with the dielectric film interposed therebetween. The portion is folded back and forth (in the height direction) several times so that a plurality of convex steps are continuous. Therefore, the occupied area of the entire capacitive element is relatively small for a large capacitance value. The capacitive element is not packaged like a single component, but is directly embedded in the wiring board. For this reason, the size in the height (wiring board thickness) direction is relatively small for a large capacitance value.

  Furthermore, in order to maintain the shape of a plurality of convex steps, the second capacitor electrode also serves as a reinforcing member. Specifically, the second capacitor electrode is formed so as to embed a concave portion between the convex steps. For this reason, the capacitive element is as if it is one integral part with high rigidity, and even if the substrate resin is filled around, the shape of the convex step is deformed and the capacitance value changes slightly. Alternatively, the leakage current of the dielectric film does not increase due to stress.

  In addition, the first capacitor electrode and the second capacitor electrode can be positioned in a planar shape on one side and the other side of the two wiring layers. Therefore, the electrode take-out structure can be easily formed and the productivity is high. Furthermore, the parasitic resistance at the time of taking out the electrode in each electrode can be reduced, and a high-performance capacitive element that maintains a desired capacitance value is formed integrally with the wiring board even when the operating frequency is particularly high.

  The method of manufacturing a wiring board according to the present invention includes a step of forming a capacitive element in one wiring layer, a step of embedding the capacitive element with a substrate resin, and the substrate resin in which the capacitive element is embedded in another wiring layer A step of pressing and bonding to each other. The capacitor element forming step includes the following four more detailed steps.

(A) A plurality of convex step members separated from each other are formed by applying a photosensitive resin, exposing and developing on a portion to be the first electrode pattern of the one wiring layer.
(B) A first capacitor electrode is formed by forming a first electrode film that covers the plurality of convex stepped members and is connected to a portion that becomes the first electrode pattern between the convex stepped members.
(C) The first electrode film having a surface on which a plurality of convex steps are continuous is covered with a dielectric film.
(D) By filling the concave portion of the dielectric film with the electrode material reflecting the surface shape of the convex step of the base, the reinforcing member for maintaining and reinforcing the surface shape of the convex step at the time of pressing is also used. A two-capacitance electrode is formed.

  In the above manufacturing method, the second capacitor electrode serves as a reinforcing member to maintain the surface shape of the convex step when pressing one wiring layer on which the capacitive element is formed with another wiring layer through the substrate resin. There is. Therefore, even after forming a large-capacity capacitive element with a small area, the wiring board can be completed while maintaining its performance.

According to the present invention, even when the capacitance value is large, the occupation area can be small, the height can be relatively small, and there is no fear of poor terminal connection, and the wiring board of the built-in capacitor element with high reliability and the built-in circuit board. Can be realized with electronic devices.
Further, according to the present invention, a capacitive element built-in type wiring substrate can be manufactured without impairing the performance and quality of the capacitive element having a small area and a large capacity.

FIG. 2 is a plan view of a wiring board incorporating a capacitive element according to the first embodiment and two cross-sectional views in different directions. It is sectional drawing in the middle of manufacture of the wiring board shown in FIG. 1, and shows even the mask layer formation which protects a MIM structure. It is sectional drawing in the middle of manufacture of the wiring board following FIG. 2, and shows to the dry film formation for 1st electrode processing. FIG. 4 is a cross-sectional view of the wiring substrate in the middle of the manufacturing process following FIG. 3 and shows the bonding of the substrate resin layer and the wiring layer. FIG. 5 is a cross-sectional view of the wiring board subsequent to FIG. 4 in the middle of manufacture, showing a contact opening for extracting an electrode. It is sectional drawing in the middle of manufacture of the wiring board in connection with 2nd Embodiment, and sectional drawing after completion. It is a figure which shows the general view of the mobile telephone in connection with 3rd Embodiment.

Embodiments of the present invention will be described in the following order with reference to the drawings.
1. First Embodiment: An embodiment in which the convex step is formed from a non-conductive material such as a photosensitive resin, and includes a first modification.
2. Second embodiment: An embodiment in which a convex step is formed from a conductive material, and includes a second modification.
3. Third modification 4. Third Embodiment: A mobile phone is shown as an example of an electronic device.

First Embodiment>
[Wiring board structure with capacitance]
FIG. 1 shows the structure of a wiring board incorporating a capacitive element according to the first embodiment of the present invention. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A, and FIG. 1C is taken along line BB in FIG. It is sectional drawing.

  A wiring board 1 illustrated in FIG. 1 is a mounting board for an electronic component in which three wiring layers are laminated between each layer via a board resin layer. In FIG. 1, a substrate resin layer 5 is disposed between a wiring layer 7 on the lowermost layer (back surface) and an intermediate wiring layer (a part of a conductive layer indicated by reference numeral “21” described later). A substrate resin layer 6 is disposed between the substrate resin layer 5 and the uppermost (surface) wiring layer (a part of the conductive portion indicated by reference numeral “8”).

  Note that the wiring board to which the present invention is applied in the first embodiment is not limited to the types of the three wiring layers and the two board resin layers in FIG. Although there are at least two wiring layers and at least one substrate resin layer, there is no limitation on the number thereof.

In FIG. 1, a capacitive element (capacitor CAP) is embedded in a substrate resin layer 6 between an intermediate wiring layer and the uppermost (surface) wiring layer. The capacitor CAP may be embedded in the substrate resin layer 5 between the wiring layer 7 and the intermediate wiring layer.
In any case, the capacitor CAP includes the first capacitor electrode 2 including the first electrode pattern 21 that is a part of the lower wiring layer, the dielectric film 3, and the second capacitor electrode 4.

The first electrode pattern 21 is a conductive layer formed together with an intermediate wiring layer, and has sufficient thickness and strength as a lower support of the capacitor CAP. Moreover, it has sufficient conductivity as the first capacitor electrode.
The first capacitor electrode 2 includes a relatively thick first electrode pattern 21 and a relatively thin first electrode film 22.

  On the upper surface of the first electrode pattern 21, a plurality (here, five) of convex step members 23 are arranged apart from each other. The convex step member 23 is made of, for example, a photosensitive resin such as a solder resist. The five convex step members 23 each have a standing long wall shape and are arranged in parallel to each other.

The first electrode film 22 is formed so as to cover the surfaces (convex step surfaces) of the five convex step members 23. Thereby, the surface (upper surface) of the first electrode film 22 is a surface in which a plurality of convex steps are continuous.
The first electrode film 22 is in contact with the underlying first electrode pattern 21 with low resistance at a portion between the adjacent convex step members 23.

The dielectric film 3 covers the convex stepped surface of the first electrode film 22.
As a dielectric material of the dielectric film 3, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, or the like can be used. The dielectric film 3 may be formed of one of these dielectric materials, a material obtained by laminating or mixing thin films of these dielectric materials, or a material obtained by adding another element to the dielectric material. You may form using.

A second electrode film 41, which is a part of the second capacitor electrode 4, is formed so as to cover the surface of the dielectric film 3 where the convex steps are continuous.
As the conductive material of the second electrode film 41 and the first electrode film 22, a metal material such as Ru, Mo, Pt, or a nitride of a metal element contained in the dielectric material, for example, hafnium nitride, zirconium nitride Conductive nitride materials such as tantalum nitride and titanium nitride can be used. Forming an electrode film with these materials is effective in preventing oxygen in the dielectric film from diffusing into one or both of the first and second electrode films 22 and 41.

  The first electrode film 22, the dielectric film 3, and the second electrode film 41 are preferably formed by an ALD (Atomic Layer Deposition) method having excellent coverage characteristics. In the case where a relatively high coverage characteristic is not required due to a relatively large separation width of the convex step member 23 or a relatively small height of the convex step member 23, etc., CVD or These films may be formed by other film forming methods such as sputtering.

The surface (upper surface) of the second electrode film 41 has a convex stepped surface shape reflecting its base shape. That is, a plurality (four in this case) of concave portions are formed on the surface of the second electrode film 41 in correspondence with the separated portions of the convex stepped member 23.
On the second electrode film 41, a reinforcing electrode member 42 filling these recesses is formed in contact with the second electrode film 41 with low resistance.

  Here, the longitudinal direction of each convex step member 23 is the direction along the line AA in FIG. 1A, and FIG. 1C is formed on the side wall surface of the one convex step member 23. It is sectional drawing of the 1st electrode pattern 21 part.

As shown in FIG. 1C, a deep contact hole 6 </ b> A that reaches the upper surface of the first electrode pattern 21 is formed in the substrate resin layer 6 on one side in the longitudinal direction of the convex stepped member 23. .
A shallow contact hole 6 </ b> B reaching the upper surface of the reinforcing electrode member 42 is formed in the substrate resin layer 6.

  As shown in FIG. 1C, the first extraction electrode 24 is formed so as to fill the deep contact hole 6A with a conductive material. The first extraction electrode 24 is embedded in a hole formed in the upper wiring layer 8 so as to communicate with the deep contact hole 6A, and is connected to the wiring by contacting the wiring layer 8 in this hole portion. Yes.

  Similarly, the second extraction electrode 43 is formed so as to bury the shallow contact hole 6B with a conductive material. The second extraction electrode 43 communicates with the shallow contact hole 6B and is buried in a hole formed in the other wiring layer 8 above, and is connected to the wiring in this hole portion.

In this way, the two electrode extraction portions (first electrode extraction portion and second electrode extraction portion) of the capacitor CAP are configured.
In FIG. 1A, the wiring layer 8 in the portion of the first extraction electrode 24 and the other wiring layer 8 in the portion of the second extraction electrode 43 are shown as rectangular isolated patterns. However, these wiring layers 8 may have a pattern in a desired direction as a wiring.

  The capacitor CAP embedded in the inside of the wiring board 1 according to this embodiment forms an MIM (Metal-Insulator-Metal) structure in which a plurality (five) of convex step members 23 are folded up and down several times. ing. For this reason, it has a large capacitance value for a small occupation area (area seen in the plane of FIG. 1A). Further, since the MIM structure is integrally formed in the wiring board, the height (thickness) is small for a large capacitance value.

  Further, like the first electrode pattern 21 and the reinforcing electrode member 4, an electrode extraction structure is formed on the planar electrode portion through two contact holes. If the conductivity of these electrode members is sufficiently high, it is possible to take out the electrode with low resistance. The parasitic resistance value at this time is sufficiently lower than the terminal connection when the electronic component is embedded in the wiring board. Also, the parasitic capacitance value and the parasitic inductance are sufficiently small. Therefore, this CAP structure can obtain desired characteristics even in a region where the frequency is particularly high.

Note that this electrode extraction structure is formed after the capacitor CAP is formed and the substrate resin layer 6 or the like is filled around the capacitor CAP. Therefore, the resistance value does not change due to the stress during resin filling. Further, one of the features of the present CAP structure is that the reinforcing electrode member 42 is formed so as to embed the concave portions of the convex step surfaces formed by the plurality of convex step members 23.
However, since these effects brought about by the structure are exhibited at the time of manufacture, details of these effects will be described later.

In the design, for example, the size is determined as follows.
Since the separation height between the embedded wiring layers is defined, the height of each convex step member 23 is determined in accordance with the separation height. Then, the number, width, separation width, and length of the convex step member 23 are determined so that a desired capacitance value is obtained. As described above, the CAP according to the present embodiment can flexibly determine a size for obtaining a desired capacitance value in accordance with the separation height between two wiring layers to be embedded.

[Method of manufacturing wiring board with capacitance]
FIG. 2A to FIG. 5C are views during manufacturing (mainly cross-sectional views corresponding to FIG. 1B) for explaining the manufacturing method of the first embodiment.

First, as shown in FIG. 2A, a core substrate which is a part of the wiring substrate 1 is formed. Here, the core substrate is a substrate portion serving as a base for forming the capacitor CAP (FIG. 1), and the wiring layer 7 and the wiring layer 21A including the first electrode pattern 21 (FIG. 1) are sandwiched between the substrate resin layers 5. It has a structure.
The core substrate is formed by, for example, a method of attaching two wiring layers having a desired wiring pattern on both surfaces of a resin sheet to be the substrate resin layer 5 or patterning after attaching a metal layer.

  Thereafter, a photosensitive resin 23A is applied to the surface of the wiring layer 21A of the core substrate with a predetermined thickness, and heat treatment or the like is performed. For example, a solder resist may be used as the photosensitive resin 23A.

  In the step of FIG. 2B, the photosensitive resin 23A is patterned by exposure and chemical treatment (development and rinsing), and a plurality of (here, five) convex step members 23 are formed on the wiring layer 21A. To form.

  In the step of FIG. 2C, the first electrode film 22, the dielectric film 3, and the second electrode film 41 are sequentially formed on the wiring layer 21A and the convex stepped member 23.

  At this time, it is desirable to use an ALD method with good step coverage as a method of forming the dielectric film 3. As the dielectric material, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, or the like can be used. The dielectric film 3 may be formed of one of these dielectric materials, a material obtained by laminating or mixing thin films of these dielectric materials, or a material obtained by adding another element to the dielectric material. You may form using.

As a method for realizing low-temperature film formation, for example, a plasma ALD method in which oxidation or nitridation is performed by plasma reaction using oxygen, ozone, or the like as an oxidization source, nitrogen, ammonia, or the like as a nitridation source can be used. In the case of an oxide film, a thermal ALD method using hydrolysis in which a reaction between an organic material containing silicon or metal and H ₂ O proceeds even at a low temperature may be used.

  Furthermore, for example, the dielectric film 3 is formed using a low-temperature plasma CVD method using a high-density plasma source such as ECR, or a low-temperature thermal CVD method using hydrolysis, which has been developed recently. You may do it.

It is desirable that the first electrode film 22 and the second electrode film 41 are formed using the ALD method with good step coverage.
Further, as the conductive material of the first electrode film 22 and the second electrode film 41, a metal material such as Ru, Mo, Pt may be used. Alternatively, the first electrode film 22 and / or the second electrode film 41 may be formed using a conductive nitride material such as a nitride of a metal element contained in the dielectric material, for example, hafnium nitride, zirconium nitride, tantalum nitride, or titanium nitride. It can also be formed.
This is effective in preventing oxygen in the dielectric film from diffusing into the first and second conductive layers 21 and 22.

  Next, as shown in FIG. 2D, for example, a mask layer 44 such as a dry film is formed slightly larger than the position where the convex step member 23 is formed. Thereby, the convex stepped member 23 and the MIM structure (the first electrode film 22, the dielectric film 3, and the second electrode film 41) thereon are protected.

  Subsequently, using the mask layer 44 as a protective layer, the surrounding second electrode film 41, dielectric film 3 and first electrode film 22 are sequentially removed by a method such as chemical treatment or dry etching.

  Next, as shown in FIG. 3A1, for example, a solder resist R1 is applied, and exposure and chemical treatment are performed. Thereby, the pattern having the opening R1a exposing the concave portion of the second electrode film 41 formed by the convex stepped member 23 is resolved in the solder resist R1.

  At this time, the opening R1a of the solder resist R1 may be outside the convex step member 23 as shown in FIG. The position and size of the opening R1a may be any as long as at least four recesses (all recesses) are exposed. Hereinafter, it is assumed that an opening R1a having a size as shown in FIG.

  Next, as shown in FIG. 3B, the reinforcing electrode member 42 is formed in the opening R1a of the formed solder resist R1 by, for example, an electroless plating method using a palladium catalyst or the like. Thereby, the capacitor CAP is formed from the MIM structure (21, 3, 41) covering the plurality of convex step members 23 formed on the first electrode pattern 21 and the reinforcing electrode member 42 thereon.

  When the plating method is used in this way, the filling property of the conductive material is good, and the reinforcing electrode member 42 is filled with no gap between the concave portions formed on the surface of the second electrode film 41 reflecting the shape of the convex stepped member 23. Is done. Further, since the reinforcing electrode member 42 is formed relatively thick in the plating method, the dielectric film 3 in which the thin second electrode film 41 alone is not sufficient in the step of opening the substrate resin layer 6 (FIG. 1) described later. It is effective in preventing damage to the skin.

  After removing the solder resist R1, as shown in FIG. 3C, a dry film DF1 or the like is formed so as to obtain a desired pattern larger than at least the MIM structure, thereby protecting the MIM structure. As the dry film DF1, a film in which a desired pattern is formed in advance may be pasted, or a film may be pasted and processed into a desired pattern.

  Subsequently, using the dry film DF1 as a mask layer, the surrounding wiring layer 21A is removed by etching. The mask layer used at this time (the portion indicated by “dry film DF1” in FIG. 3C) has a size that protects the MIM structure and secures the contact region of the first extraction electrode 24 shown in FIG. . In this etching, a circuit pattern (not shown) is formed on the wiring layer 21A other than the capacitor CAP.

  Subsequently, as shown in FIG. 4, the substrate resin layer 6 in which the capacitor CAP is embedded and the conductive layer 8A thereon are pasted by press working. At this time, further multilayering may be performed by pressing together an insulating layer and a conductive layer (not shown) on the back surface of the core substrate 11.

  In this press working, a stress in the lateral direction is applied to the plurality of convex stepped members 23 due to the flow of the substrate resin layer 6. Therefore, the space between the adjacent convex step members 23 is filled with the reinforcing electrode member 42. In order to suppress the influence due to the stress applied to the convex stepped member 23, the space between the stepped members may be filled with an insulating material, but in this embodiment, the reinforcing electrode member 42 is filled with electroless plating. Even if the reinforcing electrode member 42 is made of a relatively soft material, high rigidity is secured integrally with the plurality of convex stepped members 23, so that the convex stepped member 23 is caused by the stress caused by the flow of the substrate resin layer 6. And the MIM structure on it does not deform. Therefore, there is no increase in capacitor leakage.

  Next, as shown in FIG. 5, an opening (deep contact hole 6A) is formed near the end of the first electrode pattern 21 (corresponding to the first electrode extraction portion), and the top surface of the reinforcing electrode member 42 is An opening including a part (shallow contact hole 6B) is formed. In the formation of the deep contact hole 6A, the wiring layer 8A at that portion is removed with a laser, and then the substrate resin layer 6 is dug with the laser until the first electrode pattern 21 is exposed. In the formation of the shallow contact hole 6B, the wiring layer 8A in that portion is removed with a laser, and then the substrate resin layer 6 on the reinforcing electrode member 42 is removed with a laser.

  Note that if the size (diameter) of the deep contact hole 6A is increased more than necessary, the occupied area of the first electrode pattern 21 increases, so that the size of the deep contact hole 6A is set to a necessary size in consideration of the contact resistance. On the other hand, it is desirable that the size of the shallow contact hole 6 </ b> B is maximized on the upper surface of the reinforcing electrode member 42.

  When attention is paid to the reduction of parasitic resistance, the longitudinal direction of the protruding wall-like stepped members 23 arranged in parallel to each other is different from that of the deep contact hole 6A in FIGS. The orientation shown in C) is desirable. That is, it is desirable that the deep contact hole 6 </ b> A is disposed on one side (or both sides) in the longitudinal direction of the convex step member 23.

This is based on the following reason.
A portion of the first electrode film 22 in contact with the first electrode pattern 21 in the separation region of the convex step member 23 (four parallel line portions) has a deeper contact than a portion on the convex step member 23 on both sides thereof. The resistance value seen from the hole 6A is small.
If a deep contact hole 6A is provided in one of the four parallel line portions in the width direction, the resistance value viewed from the deep contact hole 6A is not uniform in the four parallel line portions. That is, the resistance value increases as the distance between the parallel lines increases. Further, the convex stepped member 23 closest to the deep contact hole 6A hinders the reduction in resistance. In other words, since the current path is formed so as to get over or bypass the nearest convex stepped member 23, the average current path length is increased accordingly, which hinders the overall resistance reduction.
In the present embodiment, since the deep contact hole 6A is arranged on one side in the longitudinal direction of the convex stepped members 23 arranged in parallel, the parasitic resistance of the first capacitor electrode is relatively small.

As described above, the relationship between the arrangement of the convex step member 23 and the position of the deep contact hole 6A is very important for reducing the parasitic resistance of the lower electrode of the capacitor CAP. It is essential.
In addition, lowering the resistance of the upper electrode is an important factor particularly for the capacitor CAP for high frequency applications. For this reason, in the capacitor CAP of this embodiment, a shallow contact hole 6B on the reinforcing electrode member 42 is possible in order to reduce parasitic resistance in taking out the upper electrode (the second electrode film 41 and the reinforcing electrode member 42). As wide as possible.

  Thereafter, as shown in FIG. 1, a conductive layer is formed to fill the deep contact hole 6A and the shallow contact hole 6B, for example, by electroless plating using a palladium catalyst or the like. At this time, a plating layer may be formed on the entire surface, and then the plating layer may be patterned by photolithography to separate the first extraction electrode 24 and the second extraction electrode 43. Alternatively, plating may be performed after a layer having an opening that is one size larger than the deep contact hole 6A and the shallow contact hole 6B is formed of, for example, a resist.

<First Modification>
When the reinforcing electrode member 42 is formed of a conductive material as in the present embodiment, the second electrode film 41 can be omitted. In the present embodiment, the second electrode film 41 is formed by the ALD method in consideration of the embedding characteristics. However, when the thick reinforcing electrode member 42 is formed by the ALD method, it is disadvantageous in terms of time and cost. Therefore, in the present embodiment, the second capacitor electrode 4 has a two-layer structure of the second electrode film 41 and the reinforcing electrode member 42. If there is a conductive layer forming method with good embedding characteristics other than the ALD method, the second electrode film 41 is not an essential configuration.

  In the case of the present embodiment in which the convex stepped member 23 is formed of a nonconductive material, the first electrode film 22 that constitutes a part of the first capacitor electrode 2 is essential. The first electrode film 22 is preferably formed by a film forming method such as an ALD method having high embedding characteristics.

[Effect of the first embodiment]
First, advantages of the capacitor CAP of the present embodiment will be described in comparison with a parallel plate type capacitor.

  The capacitance value of the capacitive element (capacitor or capacitor) can generally be expressed as in equation (1). Here, the symbol “C” is the capacitance value, “ε0” is the dielectric constant in vacuum, “ε” is the relative dielectric constant of the dielectric film used, “S” is the electrode area, and “T” is the film of the dielectric film. Each thickness is represented.

C = ε0 * ε * (S / T) (1)

As is clear from this equation, in a conventional capacitor having a parallel plate type electrode formed in or on the wiring board, the capacitance value is proportional to the electrode area. Therefore, in order to form a capacitor CAP having a large capacity, a large occupied area is required.
Therefore, in the conventional capacitor structure built in the wiring board, if the capacitance value is increased, the area occupied by the capacitor in the wiring board increases accordingly, and this limitation makes it difficult to reduce the size of the wiring board.

  The structure of the wiring board and the manufacturing method thereof according to this embodiment described above have the following advantages.

  First, since the plurality of convex step members 23 are formed using a photolithography technique, they can be formed with a high density by fine processing, and can be formed with very high accuracy. As a result, variations in the effective electrode area of the capacitor CAP can be suppressed, and a high-capacity capacitor CAP (that is, a capacitance value per unit occupation area is large) can be realized.

In order to increase the capacitance value per unit occupation area, it is desirable that the dielectric film 3 be made thin and formed of a material having a high relative dielectric constant.
As a second advantage, in the present embodiment, by further forming the dielectric film 3 by the ALD method, a wiring board having a built-in high-density capacitor CAP can be formed.

  Although related to the second advantage, a dielectric sheet or the like has been conventionally used as the dielectric film. However, the thickness of the sheet is several [μm], and it is difficult to secure a large capacity.

  In the present embodiment, since the dielectric film 3 is formed using the ALD method, which is a film formation method established by a semiconductor process, a dielectric film having a good embedding characteristic and a high non-dielectric constant is formed thinly, Densification can be realized.

  Furthermore, as a third advantage, as described above, the parasitic resistance, parasitic inductance, and the like during electrode extraction can be reduced as much as possible on both the first capacitor electrode side and the second capacitor electrode side. Therefore, replace high-capacity capacitors for high-frequency applications, such as those for band-pass filters and decoupling that have been used with external parts (mounting parts), with the CAPs already formed in the wiring board. Becomes easy. Such a capacitor CAP having a small parasitic element is suitable not only for high-frequency analog applications but also for high-speed digital applications.

<2. Second Embodiment>
[Wiring board structure with capacitance]
FIG. 6C shows a cross-sectional structure of the wiring board according to the second embodiment. FIG. 6 corresponds to FIG. 1B related to the first embodiment, and other portions, particularly a plan view and a cross-sectional view in another direction, are common to FIG. 1A and FIG.

  The wiring board 1 illustrated in FIG. 6C is a conductive convex made of a conductive material in place of the convex stepped member 23 formed of a nonconductive material such as a photosensitive resin in FIG. 1B. A step-like step member 25. There are three conductive convex step members 25 in FIG. 6C and fewer than the convex step members 23 in FIG. 1B, but the number is arbitrary as long as there are a plurality. When the conductive convex step member 25 is formed by plating as will be described later, the width of the convex step member is usually larger than that of the convex step member 23 formed by photolithography.

  Other capacitor configurations, that is, the underlying first electrode pattern 21, the MIM structure multilayer film (22, 3, 41) that covers the plurality of conductive convex step members 25, and the reinforcing electrode that fills the concave portion of the second electrode film 41 The material and shape of the member 42 are the same as those in the first embodiment (FIG. 1). Further, the second extraction electrode 43 connected to the reinforcing electrode member 42 and the first extraction electrode 24 (not shown) (see FIG. 1) are the same in the first and second embodiments.

[Method of manufacturing wiring board with capacitance]
6 (A) and 6 (B) are cross-sectional views of the substrate in the middle of the manufacturing method in place of the steps of FIGS. 2 (A) and 2 (B) according to the first embodiment.

As in the first embodiment, the core substrate is patterned, for example, by pasting two wiring layers having a desired wiring pattern on both surfaces of the resin sheet to be the substrate resin layer 5, or by pasting a metal layer, etc. It is formed by the method.
Subsequently, as shown in FIG. 6A, for example, a photosensitive resist R2 is applied on the wiring layer 21A formed on the surface of the substrate resin layer 5 of the core substrate, and the patterning is performed. More specifically, the resist R2 is patterned by exposure and chemical treatment (development and rinsing) to form a plurality (here, three) of openings R2a.

  Next, as shown in FIG. 6B, a conductive convex step member 25 is formed inside each opening R2a of the resist R2 by, for example, an electroless plating method using a palladium catalyst.

Thereafter, although not particularly shown, the capacitor CAP is completed by the same process as in the first embodiment.
That is, after removing the resist R2, the first electrode film 22, the dielectric film 3, and the second electrode film 41 are formed and processed, and the reinforcing electrode member 42 is formed. Then, the capacitor CAP shown in FIG. Form a structure.

  At this time, in order to reduce the parasitic resistance or the like of the upper electrode (second capacitor electrode), the interval between the conductive step structures 32 is widened, for example, a reinforcing electrode member 42 formed by electroless plating, It is effective to increase the thickness of the conductive member filled in the concave portion of the film 41.

  Thereafter, as in the first embodiment, after the substrate resin layer 6 and the wiring layer 8 are formed, the lead-out structure of the first and second capacitor electrodes is formed using a laser or the like to complete the wiring substrate 1. Let

<Second Modification>
In the second embodiment, at least one of the first electrode film 22 and the second electrode film 41 can be omitted.

The reason why the first electrode film 22 can be omitted is related to the fact that the conductive convex step member 25 has conductivity. That is, the first capacitor electrode composed of the first electrode pattern 21 and the plurality of conductive convex step members 25 formed on the first electrode pattern 21 so as to be spaced apart from each other has a shape in which a plurality of convex steps are continuous on the surface. In this sense, the first electrode film 22 can be omitted because it becomes a surface.
The reason why the second electrode film 41 can be omitted is as described in the first modification of the first embodiment.

However, when the conductive convex stepped member 25 is formed by plating, it is desirable that the first electrode film 22 exists. When the surface of the conductive convex step member 25 formed during the plating is oxidized, an interface structure is formed from metal to metal oxide and the insulator of the dielectric film 3, and the charge barrier potential change is not steep, so that leakage occurs. There are growing concerns.
On the other hand, consider a case where the first electrode film 22 made of a conductive material that is less likely to be oxidized is formed on the surface of the conductive convex stepped member 25. In this case, when the dielectric film 3 is formed on the first electrode film 22, the interface between the conductive member (first electrode film 22) and the non-conductive member (dielectric film 3) changes the charge barrier potential. As a result, the interface structure is less likely to leak.

  Note that the first electrode film 22 in this sense is not necessarily required if the conductive convex stepped member 25 is a material that is difficult to oxidize. However, if the irregularities on the surface of the conductive convex step member 25 are alleviated by the formation of the first electrode film 22, this is also effective in reducing the leakage, so that the first electrode film 22 is also interposed. Is desirable.

<3. Third Modification>
In the embodiment described so far, the convex step member 23 or the conductive convex step member 25 has one or more standing wall shapes.
However, the shape of the convex stepped member 23 or the conductive convex stepped member 25 is not limited to this. For example, if the isolated columnar steps are arranged in a matrix or checkered pattern and the capacitance value per unit occupied area is higher, such a shape may be used.

  Note that the capacitor CAP proposed by the first and second embodiments does not always define a wiring layer formed in the wiring board due to its nature. That is, although the first electrode pattern 21 is formed of the intermediate wiring layer, the first electrode pattern 21 may be provided separately from the wiring layer. Further, the first extraction electrode 24 and the reinforcing electrode member 42 may be formed not by the uppermost wiring layer but by a wiring layer inside the substrate, and a structure in which the electrode is taken out on the front surface or back surface side of the substrate may be provided.

There is no limitation on the arrangement and the number of capacitors CAP having the basic structure shown in the figure, such as by stacking a plurality of capacitors in the substrate.
Furthermore, although the electrode extraction structure was obtained by drilling by laser processing, drilling can also be performed by other processing methods such as a drill method.

<4. Third Embodiment>
The wiring boards according to the first and second embodiments and the first to third modifications described above are suitable for mounting on various electronic devices, particularly small electronic devices that handle high frequencies. Examples of such small electronic devices include notebook personal computers, mobile phones, and PDAs. Hereinafter, a mobile phone will be described as an example.

7A and 7B are diagrams showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which FIG. 7A is a front view in an opened state, FIG. 7B is a side view thereof, and FIG. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view.
The mobile phone according to this application example includes an upper casing 141, a lower casing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub-display 145, a picture light 146, a camera 147, and the like. As the display 144 and the sub-display 145, the first and second embodiments and the wiring boards according to the first to third modifications can be used.

  As described above, according to the embodiment of the present invention and the modification thereof, when a large capacity is formed by the capacitor CAP having the parallel plate type electrode structure, the adverse effect of increasing the occupied area can be avoided. . That is, in order to improve this, the electrode structure is three-dimensionally formed. Specifically, a step structure is formed on an existing conductive layer in the line substrate, and a capacitor MIM structure is formed thereon. As a result, a large-capacity capacitor CAP can be realized while controlling the occupied area, and the wiring board can be reduced in size.

  Further, as compared with the case of embedding a capacitor (capacitor component) of an electronic component inside the substrate, the size in the height (substrate thickness) direction can be reduced even when the same capacitance value is obtained. In addition, the conductive layer connection inside the capacitor CAP and the conductive layer connection in the structure in which the electrode of the capacitor CAP is taken out can be made with large surface contact. Furthermore, since the electrode extraction structure is performed after embedding the capacitor CAP with the substrate resin layer, stress is not applied to the electrode extraction structure during filling (coating) of the highly fluid substrate resin and subsequent bonding of the conductive layer. Therefore, compared with the case where the resin is filled after the electronic component is connected inside the substrate, the reliability can be increased because there is no concern about the occurrence of defective terminal connection.

  Since it has such advantages, it is particularly preferable to mount this wiring board on a small electronic device. As a result, the present invention greatly contributes to the reduction in size and thickness of electronic devices.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... 1st capacity electrode, 3 ... Dielectric film, 4 ... 2nd capacity electrode, 5, 6 ... Substrate resin layer, 6A, 6B ... Contact hole, 7, 8 ... Wiring layer, 21 ... First 1 electrode pattern, 22 ... first electrode film, 23 ... convex step member, 24 ... first extraction electrode, 25 ... conductive convex step member, 41 ... second electrode film, 42 ... reinforcing electrode member, 43 ... first 2 extraction electrode, CAP ... capacitor.

Claims (17)

A capacitor element is embedded in one of the substrate resin layers inside the substrate in which a plurality of wiring layers are stacked with the substrate resin layer interposed between the layers,
The capacitive element is
A first capacitive electrode supported by one of the wiring layers and having a surface in which a plurality of convex steps are continuous;
A dielectric film covering the surface of the first capacitor electrode;
A second capacitor that also serves as a reinforcing member that maintains and reinforces the surface shape of the convex step by being filled with the dielectric film interposed between the convex steps of the surface of the first capacitor electrode. Electrodes,
A wiring board having: Having a plurality of convex step members formed apart from each other;
2. The plurality of convex steps are formed on the electrode surface by covering the surfaces of the plurality of convex step members with the first capacitive electrode through the dielectric film. Wiring board. The wiring board according to claim 2, wherein the convex stepped member is made of a photosensitive resin. The first capacitance electrode is
A first electrode pattern;
A first electrode film that covers a surface of the plurality of convex step members formed on the first electrode pattern so as to be spaced apart from each other, and is in contact with the first electrode pattern at a separated portion of the adjacent convex step members;
The wiring board according to claim 3, comprising: Each of the plurality of convex step members has a standing long wall shape arranged in parallel with each other,
The wiring board according to claim 4, wherein an electrode extraction portion of the first electrode pattern is provided on at least one side in the longitudinal direction of the convex stepped member. The second capacitance electrode is
A second electrode film covering the convex step surface of the dielectric film reflecting the surface shape of the convex step of the first capacitor electrode as a base;
A reinforcing electrode member filled in the recess of the second electrode film;
The wiring board according to claim 2, comprising: The wiring according to claim 6, wherein an opening of the substrate resin layer is formed with a size slightly smaller than an upper surface of the reinforcing electrode member, and an electrode extraction portion of the second capacitor electrode is provided in the opening. substrate. The first capacitance electrode is
A first electrode pattern formed as part of the one wiring layer;
A plurality of electrode members formed on the first electrode pattern and spaced apart from each other, each having a convex step surface;
The wiring board according to claim 1, comprising: The wiring board according to claim 8, wherein each of the plurality of electrode members includes a metal plating layer. The first capacitor electrode is formed of a conductive material that is less oxidized than the metal of the first electrode member, covers the plurality of first electrode members, and is in contact with the portion of the first electrode pattern between the first electrode members. The first electrode film,
The wiring board according to claim 9, further comprising: Each of the plurality of convex step members has a standing long wall shape arranged in parallel with each other,
The wiring board according to claim 8, wherein an electrode extraction portion of the first electrode pattern is provided on at least one side in the longitudinal direction of the convex stepped member. The second capacitance electrode is
A second electrode film covering the convex stepped surface of the dielectric film reflecting the shape of the convex stepped surface of the first capacitor electrode as a base;
A reinforcing electrode member filled in the recess of the second electrode film;
The wiring board according to claim 11, comprising: The wiring according to claim 12, wherein an opening of the substrate resin layer is formed with a size slightly smaller than an upper surface of the reinforcing electrode member, and an electrode extraction portion of the second capacitor electrode is provided in the opening. substrate. Forming a capacitive element in one wiring layer, embedding the capacitive element with a substrate resin, and pressing and bonding another wiring layer on the substrate resin in which the capacitive element is embedded. And
In the step of forming the capacitive element,
Forming a plurality of convex stepped members separated from each other by applying a photosensitive resin, exposing and developing on a portion to be the first electrode pattern of the one wiring layer,
Forming a first capacitor electrode by forming a first electrode film that covers the plurality of convex stepped members and is connected to a portion to be the first electrode pattern between the convex stepped members;
Covering the first electrode film having a surface on which a plurality of convex steps are continuous with a dielectric film;
A second capacitor electrode that also serves as a reinforcing member that maintains and reinforces the surface shape of the convex step at the time of pressing by filling the concave portion of the dielectric film with an electrode material reflecting the surface shape of the convex step of the base A method of manufacturing a wiring board. The method for manufacturing a wiring board according to claim 14, wherein the first electrode film and the dielectric film are formed by an atomic layer deposition method. The wiring board according to claim 15, wherein when forming the second capacitor electrode, the second electrode film that coats the dielectric film is formed by atomic layer deposition, and then the recess is filled with the electrode material. Production method. An electronic device on which the wiring board according to any one of claims 1 to 13 is mounted.

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