WO2021085573A1 - Trench capacitor and trench capacitor production method - Google Patents

Trench capacitor and trench capacitor production method Download PDF

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Publication number
WO2021085573A1
WO2021085573A1 PCT/JP2020/040726 JP2020040726W WO2021085573A1 WO 2021085573 A1 WO2021085573 A1 WO 2021085573A1 JP 2020040726 W JP2020040726 W JP 2020040726W WO 2021085573 A1 WO2021085573 A1 WO 2021085573A1
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Prior art keywords
layer
thickness
trench
trench capacitor
conductive layer
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PCT/JP2020/040726
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French (fr)
Japanese (ja)
Inventor
善雄 青柳
里樹 末正
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太陽誘電株式会社
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Publication of WO2021085573A1 publication Critical patent/WO2021085573A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/33Thin- or thick-film capacitors 

Definitions

  • a thin film capacitor having a MIM structure formed by a thin film process and generating a capacitance by this MIM structure is known.
  • it is required to improve the generated capacity per unit area in order to reduce the size or increase the capacity.
  • Trench capacitors are known as thin film capacitors that can improve the generated capacity per unit area.
  • the trench capacitor includes a base material on which a large number of concavo-convex structures called trenches are formed, and a MIM structure provided so that a part of the base material extends along the trench.
  • the MIM structure is also provided in the trench extending in the thickness direction of the base material, the capacity per unit area can be improved.
  • Conventional trench capacitors are disclosed in, for example, Patent Documents 1 and 2.
  • the MIM structure since the MIM structure extends in the thickness direction of the base material, the current path in the conductive layer of the MIM structure becomes longer than that of a general thin film capacitor. As a result, the trench capacitor has a problem that the equivalent series resistance (ESR) tends to be large.
  • ESR equivalent series resistance
  • One of the objects of the present invention is to provide a trench capacitor and a method for manufacturing a trench capacitor capable of reducing the equivalent series resistance.
  • Other objects of the present invention will be made clear through the description throughout the specification.
  • the trench capacitor according to an embodiment of the present invention is sandwiched between a plurality of conductive layers and a plurality of conductive layers, and a base material having a top surface, a lower surface opposite to the upper surface, and trenches extending from the upper surface in the vertical direction.
  • a MIM structure having a dielectric layer and a plurality of conductive layers, each of which is located outside the trench and extends along the top surface, and inside the trench and along the wall surface of the trench. It has an extending second portion, and the thickness of the first portion of at least one conductive layer among the plurality of conductive layers is larger than the thickness of the second portion of the one conductive layer.
  • the present inventor has a small amount of current flowing inside the trench (that is, the second portion of the conductive layer), and a portion along the surface of the base material (that is, the conductive layer). It was found that the amount of current flowing in the first part) is large.
  • the thickness of the first portion of at least one conductive layer among the plurality of conductive layers is larger than the thickness of the second portion of the one conductive layer. As described above, the thickness of the first portion through which a large amount of current flows is increased, so that the equivalent series resistance can be effectively reduced.
  • the plurality of conductive layers include a first conductive layer located above the dielectric layer, and the thickness of the first portion of the first conductive layer is the second portion of the first conductive layer. It may be larger than the thickness of.
  • the thickness of the first portion of the first conductive layer may be twice or more and 50 times or less the thickness of the second portion of the first conductive layer.
  • the first portion of the first conductive layer may have a multilayer structure including a first layer and a second layer provided on the first layer. According to this configuration, the first layer and the second layer of the first conductive layer can be made of different materials.
  • the plurality of conductive layers include a second conductive layer located below the dielectric layer, and the thickness of the first portion of the second conductive layer is the second of the second conductive layer. It may be larger than the thickness of the portion.
  • the thickness of the first portion of the second conductive layer may be twice or more and 50 times or less the thickness of the second portion of the second conductive layer.
  • the first portion of the second conductive layer may have a multilayer structure including the first layer and the second layer provided on the first layer. According to this configuration, the first layer and the second layer of the second conductive layer can be made of different materials.
  • the conductivity of the material constituting the second layer may be higher than the conductivity of the material constituting the first layer. According to this configuration, the equivalent series resistance of the trench capacitor can be further reduced.
  • the thickness of the first portion of the first conductive layer may be larger than the thickness of the first portion of the second conductive layer.
  • One embodiment of the present invention relates to a circuit board including any of the above trench capacitors. Further, one embodiment of the present invention relates to an electronic device including the above circuit board.
  • the method for manufacturing a trench capacitor according to an embodiment of the present invention defines a step of preparing a base material having a top surface, a lower surface opposite to the upper surface, and a trench extending from the upper surface in the vertical direction, and defining the upper surface and the trench.
  • the step of forming the conductive layer of the MIM structure along the wall surface is provided, and the step of forming the conductive layer includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition.
  • the step of forming the conductive layer in this method of manufacturing a trench capacitor includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition.
  • a conductive layer is formed along the upper surface of the base material and the wall surface of the trench.
  • a conductive layer is formed only on the upper surface of the base material.
  • a trench capacitor and a method for manufacturing a trench capacitor capable of reducing the equivalent series resistance.
  • FIG. 5 is a cross-sectional view schematically showing a cross section of the trench capacitor of FIG. 1 cut along the line I.I. It is sectional drawing which shows the trench part of the trench capacitor of FIG. 1 enlarged. It is sectional drawing which enlarges and shows the trench part of the trench capacitor which concerns on another embodiment. It is sectional drawing which enlarges and shows the trench part of the trench capacitor which concerns on another embodiment.
  • FIG. 1 is a schematic plan view of the trench capacitor 1
  • FIG. 2 is a cross-sectional view schematically showing a cross section of the trench capacitor 1 cut along the I-I line.
  • FIG. 3 is an enlarged cross-sectional view showing a trench portion of the trench capacitor.
  • the trench capacitor 1 includes a base material 10, a MIM structure 20 provided on the base material 10, and a protective layer 40 provided so as to cover the MIM structure 20. ..
  • An external electrode 2 and an external electrode 3 are provided on the outside of the protective layer 40. The external electrode 2 and the external electrode 3 are electrically connected to the electrode layer constituting the MIM structure 20, as will be described in detail later.
  • the trench capacitor 1 is mounted on the circuit board by joining the external electrode 2 and the external electrode 3 to a land provided on the circuit board.
  • This circuit board can be mounted on various electronic devices.
  • the electronic device including the circuit board on which the trench capacitor 1 is mounted includes a smartphone, a mobile phone, a tablet terminal, a game console, and any other electronic device capable of including a circuit board on which the trench capacitor 1 is mounted. included.
  • FIGS. 1 and 2 the X, Y, and Z directions that are orthogonal to each other are shown.
  • the orientation and arrangement of the constituent members of the trench capacitor 1 may be described with reference to the X direction, the Y direction, and the Z direction shown in these figures.
  • the "width" direction, "length” direction, and “thickness” direction of the thin film capacitor 1 are the direction along the X-axis and the Y-axis of FIG. 1, respectively, unless otherwise understood in the context.
  • the positive direction of the Z-axis is the upward direction of the trench capacitor 1 and the negative direction of the Z-axis is defined as the upward direction of the trench capacitor 1, unless otherwise understood in the context.
  • the direction is the downward direction of the trench capacitor 1.
  • the base material 10 is made of an insulating material such as Si.
  • the base material 10 is formed in a substantially rectangular shape, and its width direction (X-axis direction) is, for example, 50 ⁇ m to 5000 ⁇ m, and its length direction (Y-axis direction) is For example, it is set to 50 ⁇ m to 5000 ⁇ m, and the dimension in the thickness direction (Z-axis direction) is set to, for example, 5 ⁇ m to 500 ⁇ m.
  • the dimensions of the base material 10 specifically shown in the present specification are merely examples, and the base material 10 can take any size.
  • the base material 10 has an upper surface 10a, a lower surface 10b on the opposite side of the upper surface 10a, a side surface 10c connecting the upper surface 10a and the lower surface 10b, and a wall portion 12 defining a trench 11 described later.
  • the base material 10 has a substantially rectangular parallelepiped shape, and in the present specification, the four surfaces connecting the upper surface 10a and the lower surface 10b of the base material 10 are collectively referred to as a side surface 10c.
  • a plurality of trenches 11 extending from the upper surface 10a of the base material 10 along the Z-axis direction are formed. Each of the plurality of trenches 11 is formed so as to have a predetermined depth in the Z-axis direction.
  • each of the plurality of trenches 11 has a substantially rectangular shape whose plan view shape is defined by a side extending along the X-axis direction and a side extending along the Y-axis direction. It is formed to be. In the illustrated embodiment, each of the plurality of trenches 11 is formed so that the side extending along the X-axis direction is shorter than the side extending along the Y-axis direction in a plan view.
  • each of the plurality of trenches 11 is formed to have a high aspect ratio in order to realize a high capacity per unit area. That is, each of the plurality of trenches 11 is formed so that the ratio of the depth (dimension in the Z-axis direction) to the width (for example, the length of the side in the X-axis direction) is large.
  • the width of each of the plurality of trenches 11 is, for example, 0.1 ⁇ m to 5 ⁇ m, and the depth thereof (dimensions in the Z-axis direction) is, for example, 1 ⁇ m to 100 ⁇ m.
  • the dimensions of the trench 11 specifically shown in the present specification are merely examples, and the trench 11 can take any dimension.
  • the shape of the trench 11 in a plan view is not limited to a rectangular shape, and the trench 11 can take any shape.
  • the trench 11 is configured such that its depth (dimensions in the Z-axis direction) is 30 ⁇ m and its width (dimensions in the X-axis direction) is 1.0 ⁇ m.
  • the trench 11 can be formed, for example, by forming a mask having openings corresponding to the pattern of the trench 11 formed on the surface of the Si substrate and then etching the Si substrate by etching.
  • the etching process of the trench 11 can be performed by a reactive ion etching method such as deep digging RIE (deep digging reactive etching) using a Bosch process.
  • adjacent trenches 11 are separated from each other by a wall portion 12.
  • the wall portion 12 is a part of the base material 10 and is configured to separate adjacent trenches 11 from each other.
  • the wall surface 13 includes a side surface 13A extending along the vertical direction (that is, the Z-axis direction) and a bottom surface 13B extending in a direction along the upper surface 10a (that is, the X-axis direction or the Y-axis direction).
  • the MIM structure 20 will be described. As described above, the base material 10 is provided with the MIM structure 20. As shown, the MIM structure 20 is provided on the base material 10 so that a part thereof is embedded in each of the trenches 11.
  • the MIM structure 20 is configured to have a shape that follows the upper surface 10a of the base material 10 and the trench 11.
  • the MIM structure 20 has a plurality of conductive layers and a dielectric layer sandwiched between the plurality of conductive layers.
  • the MIM structure 20 has a first conductive layer, a second conductive layer, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer. That is, the MIM structure 20 is a laminated body in which conductive layers and dielectric layers are alternately laminated.
  • the MIM structure 20 in the illustrated embodiment is provided on the lower electrode layer 22 (second conductive layer), the dielectric layer 21 provided on the lower electrode layer 22, and the dielectric layer 21. It also has an upper electrode layer 23 (first conductive layer).
  • the base material 10 is not used in the vertical direction along the Z-axis direction.
  • the side closer to the base material 10 may be referred to as "lower”, and the side farther from the base material 10 may be referred to as "upper”.
  • the MIM structure 20 may include two or more MIM layers.
  • a second layer is placed on the first MIM layer composed of the lower electrode layer 22, the dielectric layer 21, and the upper electrode layer 23.
  • the MIM layer of the eye is formed.
  • the second MIM layer can include a dielectric layer provided on the upper electrode layer 23 and an electrode layer provided on the dielectric layer.
  • the upper electrode layer 23 has both a function as an upper electrode layer of the first MIM layer and a function as a lower electrode layer of the second MIM layer.
  • BST barium titanate
  • BTO barium titanate
  • STO strontium titanate
  • ZrO 2 zirconia
  • Al 2 O 3 alumina
  • hafnium oxide HfO 2
  • TiO 2 Titanium oxide
  • the material of the dielectric layer 21 is not limited to those explicitly described herein.
  • the dielectric layer 21 is formed by, for example, an ALD (atomic layer deposition) method, a sputtering method, a CVD method, a vapor deposition method, a plating method, or a known method other than these.
  • the dielectric layer 21 is formed so that its film thickness is, for example, 1 nm to 500 nm. In one embodiment, the film thickness of the dielectric layer 21 is 100 nm.
  • Materials for the lower electrode 22 and the upper electrode 23 are nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), ruthenium (Ru), and tungsten (W). , Molybdenum (Mo), titanium (Ti), conductive silicon, alloy materials containing one or more of these metal elements, compounds of the metal elements, or metal materials other than these.
  • platinum (Pt) is used as the material for the lower electrode layer 22 and the upper electrode layer 23.
  • Titanium nitride (TiN) may be used as a material for the lower electrode layer 22 and the upper electrode layer 23.
  • the materials of the lower electrode layer 22 and the upper electrode layer 23 are not limited to those explicitly described herein.
  • the lower electrode layer 22 and the upper electrode layer 23 are formed by, for example, an ALD (atomic layer deposition) method, a sputtering method, a vapor deposition method, a plating method, or a known method other than these.
  • the lower electrode layer 22 is formed so that its film thickness is, for example, 1 nm to 500 nm.
  • the upper electrode 23 is formed so that its film thickness is, for example, 1 nm to 500 nm. The detailed structure of the lower electrode layer 22 and the upper electrode layer 23 will be described later.
  • the protective layer 40 is provided so as to cover the MIM structure 20 and the base material 10 in order to protect the MIM structure 20 from the external environment.
  • the protective layer 40 is provided so as to protect the MIM structure 20 from mechanical damage such as an impact received from the outside, for example.
  • a resin material such as polyimide, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and other insulating materials can be used.
  • the protective layer 40 is formed by, for example, applying a photosensitive polyimide by a spin coating method, and exposing, developing, and curing the applied polyimide.
  • the protective layer 40 is formed so that its film thickness is, for example, 200 nm to 5000 nm. In one embodiment, the film thickness of the protective layer 40 is 3000 nm. The material and film thickness of the protective layer 40 are not limited to those expressly described herein.
  • a barrier layer (not shown) may be provided between the protective layer 40 and the MIM structure 20 (or the base material 10).
  • the barrier layer is mainly provided on the MIM structure 20 in order to improve the weather resistance of the trench capacitor 1.
  • the barrier layer is provided between the MIM structure 20 and the protective layer 40 so that the moisture released from the protective layer 40 and the moisture in the atmosphere do not reach the MIM structure 20.
  • the barrier layer may be a thin film having excellent hydrogen gas barrier properties.
  • As the material of the barrier layer alumina (Al 2 O 3 ), silicon oxide (SiO 2 ), silicon oxynitride (SiON), zirconia (ZrO 2 ), and other insulating materials can be used.
  • the barrier layer is formed by, for example, a sputtering method, a CVD method, or a known method other than these.
  • the barrier layer is formed so that its film thickness is, for example, 5 nm to 500 nm. In one embodiment, the film thickness of the barrier layer is 50 nm.
  • the material and film thickness of the barrier layer are not limited to those expressly described herein.
  • the external electrode 2 and the external electrode 3 are provided on the upper side of the protective layer 40 so as to be separated from each other in the Y-axis direction.
  • the external electrode 2 and the external electrode 3 are formed by applying a conductor paste containing a metal material to the outside of the protective layer 40.
  • Materials of the external electrode 2 and the external electrode 3 include copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or other materials.
  • a metal material or an alloy material containing one or more of these metal elements can be used.
  • At least one of a solder barrier layer and a solder leakage layer may be formed on the external electrode 2 and the external electrode 3, if necessary.
  • a groove 41 is provided near the end of the protective layer 40 in the negative direction of the Y axis, and a groove 42 is provided near the end of the protective layer 40 in the positive direction of the Y axis. Both the groove 41 and the groove 42 are provided so as to extend along the X-axis direction and penetrate the protective layer 40 in the Z-axis direction.
  • the groove 41 is provided with an extraction electrode 2a, and the groove 42 is provided with an extraction electrode 3a.
  • the upper end of the extraction electrode 2a is connected to the external electrode 2, and the lower end of the extraction electrode 2a is connected to the lower electrode layer 22 of the MIM structure 20.
  • the upper end of the extraction electrode 3a is connected to the external electrode 3, and the lower end of the extraction electrode 3a is connected to the upper electrode 23 of the MIM structure 20.
  • the material of the extraction electrodes 2a and 3a copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or a metal material other than these. , Or an alloy material containing one or more of these metal elements can be used.
  • the extraction electrodes 2a and 3a are formed by a vapor deposition method, a sputtering method, a plating method, or a known method other than these.
  • each of the lower electrode layer 22 and the upper electrode layer 23 is located outside the trench 11 and is located inside the trench 11 as well as the first portions 22R1, 23R1 extending along the upper surface 10a. It has a second portion 22R2, 23R2 extending along the wall surface 13 of the trench 11. The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is larger than the thickness 23T2 of the second portion 23R2 of the upper electrode 23.
  • the thicknesses 22T1, 23T1 of the first portion 22R1, 23R1 refer to the dimensions of the lower electrode layer 22 or the upper electrode layer 23 in the Z-axis direction, respectively.
  • the thicknesses 22T2 and 23T2 of the second portions 22R2 and 23R2 refer to the dimensions of the lower electrode layer 22 or the upper electrode layer 23 in the direction perpendicular to the wall surface 13 of the wall portion 12, respectively.
  • the thickness of the portion of the second portion 22R2, 23R2 along the bottom surface 13B of the trench 11 refers to the dimension of the lower electrode layer 22 or the upper electrode layer 23 in the Z-axis direction, and the second portion 22R2, 23R2.
  • the thickness of the portion along the side surface 13A of the trench 11 refers to the dimension of the lower electrode layer 22 or the upper electrode layer 23 in the X-axis or Y-axis direction.
  • the half of the distance between the dielectric layers 21 in the X-axis direction or the Y-axis direction is the thickness 23T2 of the second portion 23R2.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 can be, for example, twice or more and 50 times or more the thickness of the second portion 23T2.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is preferably 2.5 times or more the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is 200 nm
  • the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23 is 50 nm.
  • the first portion 23R1 of the upper electrode layer 23 has a multilayer structure including a first layer 23A and a second layer 23B provided on the first layer 23A.
  • the number of layers constituting the first portion 23R1 of the upper electrode layer 23 is not particularly limited, and the first portion 23R1 may have a multilayer structure of three or more layers.
  • the first portion 23R1 of the upper electrode layer 23 is composed of two layers, the first layer 23A and the second layer 23B, and the second portion 23R2 is composed of only the first layer 23A.
  • the first layer 23A of the upper electrode layer 23 is in contact with the dielectric layer 21, and the second layer 23B of the upper electrode layer 23 is in contact with the protective layer 40.
  • the thickness of the first layer 23A is substantially the same as the thickness T2 of the second portion 23R2.
  • the thickness of the first layer 23A is, for example, 50 nm
  • the thickness of the second layer 23B is, for example, 150 nm.
  • the first layer 23A and the second layer 23B may be made of the same material as each other, or may be made of different materials from each other. In the illustrated embodiment, the first layer 23A and the second layer 23B are made of different materials, and the conductivity of the material constituting the second layer 23B is higher than the conductivity of the material constituting the first layer 23A. It has become.
  • the first layer 23A and the second layer 23B are made of different materials, the first layer 23A and the second layer 23B are combined in order to improve the adhesion between the first layer 23A and the second layer 23B.
  • An adhesion layer may be provided between them.
  • the material constituting the adhesion layer include Ti, TiN, Ta, TaN and the like.
  • the first layer 23A is composed of Pt and the second layer 23B is composed of Cu.
  • the adhesion layer between the first layer 23A and the second layer 23B is composed of Ti.
  • the thickness of the first portion 22R1 of the lower electrode layer 22 and the thickness of the second portion 22R2 of the lower electrode layer 22 are substantially the same.
  • the first portion 22R1 of the lower electrode layer 22 does not have a multi-layer structure and is composed of only one layer.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is larger than the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22.
  • the thickness of the lower electrode layer 22 is 50 nm.
  • the film thicknesses of the lower electrode layer 22 and the upper electrode layer 23 are not limited to those explicitly described herein.
  • a base material having an upper surface 10a, a lower surface opposite to the upper surface 10a, and a trench 11 extending from the upper surface 10a along the vertical direction is prepared.
  • a wafer to be the base material 10 is prepared, and a mask corresponding to the pattern of the trench 11 is formed on the upper surface of the wafer.
  • the wafer is etched to form a plurality of trenches 11.
  • Wafer etching is performed by dry etching using, for example, a Bosch process.
  • the step of forming the MIM structure 20 includes a step of forming a conductive layer and a step of forming a dielectric layer.
  • the lower electrode layer 22 is formed.
  • the lower electrode layer 22 is formed of, for example, Pt.
  • the dielectric layer 21 is formed on the lower electrode layer 22.
  • the dielectric layer 21 is formed from, for example, zirconia.
  • the lower electrode layer 22 and the dielectric layer 21 can be formed by a chemical vapor deposition method such as an ALD method or a CVD method.
  • the upper electrode layer 23 is formed on the dielectric layer 21.
  • the step of forming the upper electrode layer 23 includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition.
  • the first layer 23A is first formed by performing chemical vapor deposition such as an ALD method or a CVD method.
  • the second layer 23B is formed by performing physical vapor deposition such as a sputtering method or a vacuum vapor deposition method.
  • the thickness of the first portion 23R1 along the upper surface 10a of the base material 10 is larger than the thickness of the second portion 23R2 extending along the wall surface 13 of the trench 11.
  • the MIM structure 20 is formed by the above steps.
  • the protective layer 40 is formed on the MIM structure 20.
  • grooves are provided near both ends in the Y-axis direction of the portion of the protective layer 40 provided on the upper side of the MIM structure 20.
  • the extraction electrodes 2a and 3a are formed inside the groove by a plating method or the like, and the external electrode 2 and the external electrode 3 are formed on the surface of the protective layer 40.
  • the wafer is fragmented.
  • each of the lower electrode layer 22 and the upper electrode layer 23 (that is, the plurality of conductive layers) of the trench capacitor 1 is located outside the trench 11 and extends along the upper surface 10a. It has a 23R1 and a second portion 22R2, 23R1 that is located in the trench 11 and extends along the wall surface 13 of the trench 11, and the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is the upper electrode layer. The thickness of the second portion 23R2 of 23 is larger than the thickness 23T2.
  • the present inventor has a small amount of current flowing inside the trench (that is, the second portion 22R2, 23R2), and the substrate has a small amount of current. It has been found that the amount of current flowing in the portion along the surface (that is, the first portion 22R1, 23R1) is large. Therefore, in the trench capacitor 1, the thickness 23T1 of the first portion 23R1 of at least one conductive layer (upper electrode layer 23 in the illustrated embodiment) among the lower electrode layer 22 and the upper electrode layer 23 is set to the one. The thickness of the second portion 23R2 of the conductive layer (that is, the upper electrode layer 23) is made larger than the thickness 23T2.
  • the equivalent series resistance can be reduced.
  • the cross-sectional area of the current path can be increased without increasing the size of the trench 11 in the direction along the upper surface 10a. Therefore, it is possible to reduce the equivalent series resistance while maintaining the generated capacity per unit area.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is twice or more and 50 times or less the thickness of the second portion 23R2 of the upper electrode layer 23.
  • the equivalent series resistance can be effectively reduced.
  • the trench 11 is blocked in the step of forming the second layer 23B by the physical vapor deposition method in the manufacturing process. It is possible to prevent it from coming off.
  • the first portion 23R1 of the upper electrode layer 23 has a multilayer structure including a first layer 23A and a second layer 23B provided on the first layer 23A.
  • the first layer 23A and the second layer 23B can be made of different materials.
  • the second layer 23B having a relatively large thickness can be formed by a method having a high film forming rate.
  • the conductivity of the material constituting the second layer 23B is higher than the conductivity of the material constituting the first layer 23A. Thereby, the equivalent series resistance of the trench capacitor 1 can be further reduced.
  • the step of forming the upper electrode 23 includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition.
  • the step of performing chemical vapor deposition the first layer 23A of the upper electrode 23 is formed along the upper surface 10a of the base material 10 and the wall surface of the trench 11.
  • the step of performing physical vapor deposition it is difficult to supply the material of the second layer 23B into the trench 11, so that the second layer 23B is formed on the upper surface 10a of the base material 10.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 located outside the trench 11 and extending along the upper surface 10a is located inside the trench 11 and extends along the wall surface 13 of the trench 11.
  • the thickness of the second portion 23R2 of the layer 23 can be made larger than the thickness 23T2. Therefore, the cross-sectional area of the current path can be increased without enlarging the size of the trench 11 in the direction along the upper surface 10a (that is, the direction orthogonal to the vertical direction), and the generated capacity per unit area can be maintained.
  • the equivalent series resistance can be reduced.
  • the trench capacitor 100 according to another embodiment has a base material 10 having a trench 11 extending from the upper surface 10a and a plurality of conductive layers (that is, an upper electrode layer 23), similarly to the trench capacitor 1. And a lower electrode 22), and a MIM structure 20 having a dielectric layer 21 sandwiched between a plurality of conductive layers and provided along a wall surface 13 defining an upper surface 10a and a trench 11. ..
  • the difference between the trench capacitor 100 and the trench capacitor 1 is that the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 is larger than the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22 instead of the upper electrode layer 23. It is a point that is getting bigger.
  • the first portion 22R1 of the lower electrode layer 22 of the trench capacitor 100 has a multilayer structure, and includes the first layer 22A and the second layer 22B.
  • the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 is set within a range of twice or more and 50 times or less the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22.
  • the thickness 22T1 of the first portion 22R1 is preferably 2.5 times or more the thickness 22T2 of the second portion 22R2.
  • the thickness 22T1 of the first portion 22R1 is 200 nm
  • the thickness 22T2 of the second portion 22R2 is 50 nm.
  • the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 of the trench capacitor 100 and the thickness 23T1 of the second portion 23R2 of the upper electrode layer 23 are substantially the same.
  • the trench capacitor 100 can be manufactured by substantially the same method as the method for manufacturing the trench capacitor 1 described above, but in the step of forming the lower electrode layer 22, the first of the lower electrode layer 22 is produced by the chemical vapor deposition method. The difference is that after the layer 22A is formed, the second layer 22B of the lower electrode layer 22 is formed by the physical vapor deposition method.
  • the upper electrode layer 23 is formed by a chemical vapor deposition method such as an ALD method or a CVD method.
  • the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 is thicker than the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22. Therefore, for the same reason as that of the trench capacitor 1, it is possible to reduce the equivalent series resistance while maintaining the generated capacity per unit area.
  • the trench capacitor 200 includes a base material 10 having a trench 11 extending from the upper surface 10a and a plurality of conductive layers (that is, an upper electrode layer 23 and a lower electrode 22), similarly to the trench capacitor 1.
  • a MIM structure 20 having a dielectric layer 21 sandwiched between a plurality of conductive layers and provided along a wall surface defining an upper surface 10a and a trench 11 is provided.
  • the difference between the trench capacitor 200 and the trench capacitor 1 is that in both the upper electrode layer 23 and the lower electrode layer 22, the thickness 22T1,23T1 of the first portion 22R1,23R1 is the thickness 22T2 of the second portion 22R2,23R2.
  • the first portion 22R1 of the lower electrode layer 22 of the trench capacitor 200 has a multilayer structure, and includes the first layer 22A and the second layer 22B.
  • the first portion 23R1 of the upper electrode layer 23 also has a multilayer structure, and includes the first layer 23A and the second layer 23B.
  • the thickness 22T1,23T1 of the first portion 22R1,23R1 of the lower electrode layer 22 and the upper electrode layer 23 is set within a range of 2 times or more and 50 times or less of the thickness 22T2, 23T2 of the second portion 22R2, 23R2. .. In the embodiment shown in FIG.
  • the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 and the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 are substantially the same, but the thickness of the lower electrode layer 22 is the same.
  • the thickness 22T1 of the one portion 22R1 and the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 may be different from each other.
  • the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22 and the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23 are substantially the same, but the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22.
  • the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23 may be different from each other.
  • the thickness 22T1,23T1 of the first portion 22R1,23R1 is thicker than the thickness 22T2,23T2 of the second portion 22R2,23R2. ing. Therefore, for the same reason as that of the trench capacitor 1, it is possible to further reduce the equivalent series resistance while maintaining the generated capacity per unit area.
  • each component described herein is not limited to those expressly described in the embodiments, and each component may be included within the scope of the present invention. Can be transformed to have the dimensions, materials, and arrangement of.
  • components not explicitly described in the present specification may be added to the described embodiments, or some of the components described in each embodiment may be omitted.
  • the one object when it is described that one object is provided “above”, “upper surface”, “lower”, or “lower surface” of another object, the one object is referred to as the other object. It may be in direct contact, or may be indirect contact via another layer or membrane.
  • Trench capacitor 10 ... Base material, 10a ... Top surface, 11 ... Trench, 12 ... Wall, 20 ... MIM structure, 21 ... Dielectric layer, 22 ... Lower electrode layer (second conductive layer), 23 ... Upper Electrode layer (first conductive layer), 22A, 23A ... 1st layer, 22B, 23B ... 2nd layer, 22R1, 23R1 ... 1st part, 22R2, 23R2 ... 2nd part.

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Abstract

Provided are a trench capacitor and a trench capacitor production method which can achieve a reduction in the equivalent series resistance. This trench capacitor 1 is provided with: a base material 10 which has a trench 11 extending in the vertical direction from a top surface 10a; and an MIM structure 20 which has a plurality of conductive layers (lower electrode layer 22 and upper electrode layer 23) and a dielectric layer 21 sandwiched between the plurality of conductive layers. The plurality of conductive layers each have a first portion 22R1, 23R1 that is located outside the trench 11 and extends along the top surface 10a, and a second portion 22R2, 23R2 that is located inside the trench 11 and extends along the wall surfaces 13 of the trench 11. The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is greater than the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23.

Description

トレンチキャパシタ及びトレンチキャパシタの製造方法Trench capacitor and manufacturing method of trench capacitor
 相互参照
本出願は、日本国特許出願2019-197136(2019年10月30
日出願)に基づく優先権を主張し、その内容は参照により全体として本明細
書に組み込まれる。
 本発明は、トレンチキャパシタ及びトレンチキャパシタの製造方法に関する。
Cross-reference <br /> This application is a Japanese patent application 2019-197136 (October 30, 2019).
Priority is claimed under (Japanese filing), the contents of which are incorporated herein by reference in their entirety.
The present invention relates to a trench capacitor and a method for manufacturing a trench capacitor.
 キャパシタの一種として、薄膜プロセスにより形成されたMIM構造体を備え、このMIM構造体により容量を発生させる薄膜キャパシタが知られている。薄膜キャパシタにおいては、小型化又は高容量化のために、単位面積あたりの発生容量を向上させることが求められている。 As a kind of capacitor, a thin film capacitor having a MIM structure formed by a thin film process and generating a capacitance by this MIM structure is known. In thin film capacitors, it is required to improve the generated capacity per unit area in order to reduce the size or increase the capacity.
 単位面積あたりの発生容量を向上させることが可能な薄膜キャパシタとして、トレンチキャパシタが知られている。トレンチキャパシタは、トレンチと呼ばれる凹凸構造が多数形成された基材と、その一部がトレンチに沿って延伸するように設けられたMIM構造体と、を備えている。トレンチキャパシタにおいては、基材の厚さ方向に延びるトレンチ内にもMIM構造体が設けられるため、単位面積当たりの容量を向上させることができる。従来のトレンチキャパシタは、例えば、特許文献1及び2に開示されている。 Trench capacitors are known as thin film capacitors that can improve the generated capacity per unit area. The trench capacitor includes a base material on which a large number of concavo-convex structures called trenches are formed, and a MIM structure provided so that a part of the base material extends along the trench. In the trench capacitor, since the MIM structure is also provided in the trench extending in the thickness direction of the base material, the capacity per unit area can be improved. Conventional trench capacitors are disclosed in, for example, Patent Documents 1 and 2.
特開2008-251724号公報Japanese Unexamined Patent Publication No. 2008-251724 特開2008-251725号公報Japanese Unexamined Patent Publication No. 2008-251725
 トレンチキャパシタにおいては、MIM構造体が基材の厚さ方向にも延伸しているので、一般的な薄膜キャパシタに比べてMIM構造体の導電層における電流経路が長くなる。その結果、トレンチキャパシタでは、等価直列抵抗(ESR)が大きくなりやすいという問題がある。 In the trench capacitor, since the MIM structure extends in the thickness direction of the base material, the current path in the conductive layer of the MIM structure becomes longer than that of a general thin film capacitor. As a result, the trench capacitor has a problem that the equivalent series resistance (ESR) tends to be large.
 本発明の目的の一つは、等価直列抵抗の低下を図ることが可能なトレンチキャパシタ及びトレンチキャパシタの製造方法を提供することである。本発明のこれ以外の目的は、明細書全体の記載を通じて明らかにされる。 One of the objects of the present invention is to provide a trench capacitor and a method for manufacturing a trench capacitor capable of reducing the equivalent series resistance. Other objects of the present invention will be made clear through the description throughout the specification.
 本発明の一実施形態に係るトレンチキャパシタは、上面、上面とは反対側の下面、及び上下方向に沿って上面から延びるトレンチを有する基材と、複数の導電層及び複数の導電層に挟まれた誘電体層を有するMIM構造体と、を備え、複数の導電層のそれぞれは、トレンチ外に位置すると共に上面に沿って延びる第1部分と、トレンチ内に位置すると共にトレンチの壁面に沿って延びる第2部分と、を有し、複数の導電層のうち、少なくとも一の導電層の第1部分の厚さは、当該一の導電層の第2部分の厚さより大きい。 The trench capacitor according to an embodiment of the present invention is sandwiched between a plurality of conductive layers and a plurality of conductive layers, and a base material having a top surface, a lower surface opposite to the upper surface, and trenches extending from the upper surface in the vertical direction. A MIM structure having a dielectric layer and a plurality of conductive layers, each of which is located outside the trench and extends along the top surface, and inside the trench and along the wall surface of the trench. It has an extending second portion, and the thickness of the first portion of at least one conductive layer among the plurality of conductive layers is larger than the thickness of the second portion of the one conductive layer.
 本発明者は、トレンチキャパシタのMIM構造体の導電層においては、トレンチの内部(すなわち、導電層の第2部分)に流れる電流量が少なく、基材の表面に沿った部分(すなわち、導電層の第1部分)に流れる電流量が多いことを見出した。上記のトレンチキャパシタでは、複数の導電層のうち、少なくとも一の導電層の第1部分の厚さは、当該一の導電層の第2部分の厚さより大きい。このように、多くの電流が流れる第1部分の厚さが大きくなっていることにより、効果的に等価直列抵抗の低下を図ることができる。 In the conductive layer of the MIM structure of the trench capacitor, the present inventor has a small amount of current flowing inside the trench (that is, the second portion of the conductive layer), and a portion along the surface of the base material (that is, the conductive layer). It was found that the amount of current flowing in the first part) is large. In the above trench capacitor, the thickness of the first portion of at least one conductive layer among the plurality of conductive layers is larger than the thickness of the second portion of the one conductive layer. As described above, the thickness of the first portion through which a large amount of current flows is increased, so that the equivalent series resistance can be effectively reduced.
 本発明の一実施形態において、複数の導電層は、誘電体層の上に位置する第1導電層を含み、第1導電層の第1部分の厚さは、第1導電層の第2部分の厚さより大きくてもよい。 In one embodiment of the present invention, the plurality of conductive layers include a first conductive layer located above the dielectric layer, and the thickness of the first portion of the first conductive layer is the second portion of the first conductive layer. It may be larger than the thickness of.
 本発明の一実施形態において、第1導電層の第1部分の厚さは、第1導電層の第2部分の厚さの2倍以上且つ50倍以下であってもよい。 In one embodiment of the present invention, the thickness of the first portion of the first conductive layer may be twice or more and 50 times or less the thickness of the second portion of the first conductive layer.
 本発明の一実施形態において、第1導電層の第1部分は、第1層と、第1層の上に設けられた第2層と、を含む多層構造を有してもよい。この構成によれば、第1導電層の第1層及び第2層を互いに異なる材料によって構成することができる。 In one embodiment of the present invention, the first portion of the first conductive layer may have a multilayer structure including a first layer and a second layer provided on the first layer. According to this configuration, the first layer and the second layer of the first conductive layer can be made of different materials.
 本発明の一実施形態において、複数の導電層は、誘電体層の下に位置する第2導電層を含み、第2導電層の第1部分の厚さは、第2導電層の前記第2部分の厚さより大きくてもよい。 In one embodiment of the present invention, the plurality of conductive layers include a second conductive layer located below the dielectric layer, and the thickness of the first portion of the second conductive layer is the second of the second conductive layer. It may be larger than the thickness of the portion.
 本発明の一実施形態において、第2導電層の第1部分の厚さは、第2導電層の第2部分の厚さの2倍以上且つ50倍以下であってもよい。 In one embodiment of the present invention, the thickness of the first portion of the second conductive layer may be twice or more and 50 times or less the thickness of the second portion of the second conductive layer.
 本発明の一実施形態において、第2導電層の第1部分は、第1層と、第1層の上に設けられた第2層と、を含む多層構造を有してもよい。この構成によれば、第2導電層の第1層及び第2層を互いに異なる材料によって構成することができる。 In one embodiment of the present invention, the first portion of the second conductive layer may have a multilayer structure including the first layer and the second layer provided on the first layer. According to this configuration, the first layer and the second layer of the second conductive layer can be made of different materials.
 本発明の一実施形態において、第2層を構成する材料の導電率は、第1層を構成する材料の導電率より高くてもよい。この構成によれば、トレンチキャパシタの等価直列抵抗を更に低下させることができる。 In one embodiment of the present invention, the conductivity of the material constituting the second layer may be higher than the conductivity of the material constituting the first layer. According to this configuration, the equivalent series resistance of the trench capacitor can be further reduced.
 本発明の一実施形態において、第1導電層の第1部分の厚さは、第2導電層の第1部分の厚さより大きくてもよい。 In one embodiment of the present invention, the thickness of the first portion of the first conductive layer may be larger than the thickness of the first portion of the second conductive layer.
 本発明の一実施形態は、上記の何れかのトレンチキャパシタを備える回路基板に関する。また、本発明の一実施形態は、上記の回路基板を備える電子機器に関する。 One embodiment of the present invention relates to a circuit board including any of the above trench capacitors. Further, one embodiment of the present invention relates to an electronic device including the above circuit board.
 本発明の一実施形態に係るトレンチキャパシタの製造方法は、上面、上面とは反対側の下面、及び上下方向に沿って上面から延びるトレンチを有する基材を準備する工程と、上面及びトレンチを画定する壁面に沿ってMIM構造体の導電層を形成する工程と、を備え、導電層を形成する工程は、化学気相成長を行う工程と、物理気相成長を行う工程とを含む。 The method for manufacturing a trench capacitor according to an embodiment of the present invention defines a step of preparing a base material having a top surface, a lower surface opposite to the upper surface, and a trench extending from the upper surface in the vertical direction, and defining the upper surface and the trench. The step of forming the conductive layer of the MIM structure along the wall surface is provided, and the step of forming the conductive layer includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition.
 このトレンチキャパシタの製造方法の導電層を形成する工程は、化学気相成長を行う工程と、物理気相成長を行う工程と、を含む。化学気相成長を行う工程では、基材の上面及びトレンチの壁面に沿って導電層が形成される。一方、物理気相成長を行う工程では、基材の上面にのみ導電層が形成される。これにより、上面に沿って延びる導電層の第1部分の厚さは、トレンチ内に位置すると共にトレンチの壁面に沿って延びる導電層の第2部分の厚さより大きくすることができる。したがって、電流経路の断面積を大きくすることができ、等価直列抵抗の低下を図ることができる。 The step of forming the conductive layer in this method of manufacturing a trench capacitor includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition. In the step of chemical vapor deposition, a conductive layer is formed along the upper surface of the base material and the wall surface of the trench. On the other hand, in the step of performing physical vapor deposition, a conductive layer is formed only on the upper surface of the base material. Thereby, the thickness of the first portion of the conductive layer extending along the upper surface can be made larger than the thickness of the second portion of the conductive layer located in the trench and extending along the wall surface of the trench. Therefore, the cross-sectional area of the current path can be increased, and the equivalent series resistance can be reduced.
 本発明によれば、等価直列抵抗の低下を図ることが可能なトレンチキャパシタ及びトレンチキャパシタの製造方法が提供される。 According to the present invention, there is provided a trench capacitor and a method for manufacturing a trench capacitor capable of reducing the equivalent series resistance.
一実施形態に係るトレンチキャパシタの模式的な平面図である。It is a schematic plan view of the trench capacitor which concerns on one Embodiment. 図1のトレンチキャパシタをI-I線で切断した断面を模式的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a cross section of the trench capacitor of FIG. 1 cut along the line I.I. 図1のトレンチキャパシタのトレンチ部分を拡大して示す断面図である。It is sectional drawing which shows the trench part of the trench capacitor of FIG. 1 enlarged. 他の実施形態に係るトレンチキャパシタのトレンチ部分を拡大して示す断面図である。It is sectional drawing which enlarges and shows the trench part of the trench capacitor which concerns on another embodiment. 他の実施形態に係るトレンチキャパシタのトレンチ部分を拡大して示す断面図である。It is sectional drawing which enlarges and shows the trench part of the trench capacitor which concerns on another embodiment.
 以下、適宜図面を参照し、本発明の様々な実施形態を説明する。なお、複数の図面において共通する構成要素には当該複数の図面を通じて同一の参照符号が付される。各図面は、説明の便宜上、必ずしも正確な縮尺で記載されているとは限らない点に留意されたい。特に、後述する電極層や誘電体層は、実際には非常に薄い膜であるが、各図面においては、説明の便宜のために視認できる程度の厚さを有するように記載されている。 Hereinafter, various embodiments of the present invention will be described with reference to the drawings as appropriate. The components common to the plurality of drawings are designated by the same reference numerals throughout the plurality of drawings. It should be noted that each drawing is not always drawn to the correct scale for convenience of explanation. In particular, the electrode layer and the dielectric layer, which will be described later, are actually very thin films, but in each drawing, they are described so as to have a thickness that can be visually recognized for convenience of explanation.
 図1~図3を参照して、一実施形態によるトレンチキャパシタ1について説明する。これらの図に示されているトレンチキャパシタ1は、薄膜プロセスにより作製されたMIM構造体を有する薄膜キャパシタである。図1は、トレンチキャパシタ1の模式的な平面図であり、図2は、トレンチキャパシタ1をI-I線で切断した断面を模式的に示す断面図である。図3は、トレンチキャパシタのトレンチ部分を拡大して示す断面図である。 The trench capacitor 1 according to one embodiment will be described with reference to FIGS. 1 to 3. The trench capacitor 1 shown in these figures is a thin film capacitor having a MIM structure produced by a thin film process. FIG. 1 is a schematic plan view of the trench capacitor 1, and FIG. 2 is a cross-sectional view schematically showing a cross section of the trench capacitor 1 cut along the I-I line. FIG. 3 is an enlarged cross-sectional view showing a trench portion of the trench capacitor.
 図示のように、一実施形態によるトレンチキャパシタ1は、基材10と、基材10に設けられたMIM構造体20と、MIM構造体20を覆うように設けられた保護層40と、を備える。保護層40の外側には、外部電極2及び外部電極3が設けられる。外部電極2及び外部電極3は、詳しくは後述するように、MIM構造体20を構成する電極層と電気的に接続される。 As shown in the figure, the trench capacitor 1 according to one embodiment includes a base material 10, a MIM structure 20 provided on the base material 10, and a protective layer 40 provided so as to cover the MIM structure 20. .. An external electrode 2 and an external electrode 3 are provided on the outside of the protective layer 40. The external electrode 2 and the external electrode 3 are electrically connected to the electrode layer constituting the MIM structure 20, as will be described in detail later.
 トレンチキャパシタ1は、外部電極2及び外部電極3を回路基板に設けられたランドに接合することにより、当該回路基板に実装される。この回路基板は、様々な電子機器に搭載され得る。トレンチキャパシタ1が実装された回路基板を備える電子機器には、スマートフォン、携帯電話、タブレット端末、ゲームコンソール、及びこれら以外のトレンチキャパシタ1が実装された回路基板を備えることができる任意の電子機器が含まれる。 The trench capacitor 1 is mounted on the circuit board by joining the external electrode 2 and the external electrode 3 to a land provided on the circuit board. This circuit board can be mounted on various electronic devices. The electronic device including the circuit board on which the trench capacitor 1 is mounted includes a smartphone, a mobile phone, a tablet terminal, a game console, and any other electronic device capable of including a circuit board on which the trench capacitor 1 is mounted. included.
 図1及び図2においては、互い直交するX方向、Y方向、及びZ方向が示されている。本明細書においては、これらの図に示されているX方向、Y方向、及びZ方向を基準としてトレンチキャパシタ1の構成部材の向きや配置を説明することがある。具体的には、文脈上別に解される場合を除き、薄膜キャパシタ1の「幅」方向、「長さ」方向、及び「厚さ」方向はそれぞれ、図1のX軸に沿う方向、Y軸に沿う方向、及びZ軸に沿う方向とする。本明細書においてトレンチキャパシタ1及びその構成部材の上下方向に言及する際には、文脈上別に解される場合を除き、Z軸の正方向がトレンチキャパシタ1の上方向とされ、Z軸の負方向がトレンチキャパシタ1の下方向とされる。 In FIGS. 1 and 2, the X, Y, and Z directions that are orthogonal to each other are shown. In the present specification, the orientation and arrangement of the constituent members of the trench capacitor 1 may be described with reference to the X direction, the Y direction, and the Z direction shown in these figures. Specifically, the "width" direction, "length" direction, and "thickness" direction of the thin film capacitor 1 are the direction along the X-axis and the Y-axis of FIG. 1, respectively, unless otherwise understood in the context. The direction along the Z axis and the direction along the Z axis. When referring to the vertical direction of the trench capacitor 1 and its constituent members in the present specification, the positive direction of the Z-axis is the upward direction of the trench capacitor 1 and the negative direction of the Z-axis is defined as the upward direction of the trench capacitor 1, unless otherwise understood in the context. The direction is the downward direction of the trench capacitor 1.
 一実施形態において、基材10は、Si等の絶縁材料から成る。一実施形態において、基材10は、概ね直方体の形状に形成されており、その幅方向(X軸方向)の寸法は例えば50μm~5000μmとされ、その長さ方向(Y軸方向)の寸法は例えば50μm~5000μmとされ、その厚さ方向(Z軸方向)の寸法は例えば5μm~500μmとされる。本明細書において具体的に示される基材10の寸法は例示に過ぎず、基材10は任意の寸法をとることができる。 In one embodiment, the base material 10 is made of an insulating material such as Si. In one embodiment, the base material 10 is formed in a substantially rectangular shape, and its width direction (X-axis direction) is, for example, 50 μm to 5000 μm, and its length direction (Y-axis direction) is For example, it is set to 50 μm to 5000 μm, and the dimension in the thickness direction (Z-axis direction) is set to, for example, 5 μm to 500 μm. The dimensions of the base material 10 specifically shown in the present specification are merely examples, and the base material 10 can take any size.
 基材10は、上面10aと、当該上面10aとは反対側の下面10bと、上面10aと下面10bとを接続する側面10cと、後述のトレンチ11を画定する壁部12とを有する。図1の実施形態において基材10は略直方体状であり、本明細書中では、当該基材10の上面10aと下面10bとを接続する4つの面をまとめて側面10cという。基材10には、その上面10aからZ軸方向に沿って延伸する複数のトレンチ11が形成されている。複数のトレンチ11の各々は、Z軸方向に所定の深さを有するように形成される。本明細書においては、Z軸方向をトレンチ11の深さ方向と呼ぶことがある。図1に示されているように、複数のトレンチ11の各々は、その平面視の形状が、X軸方向に沿って延びる辺とY軸方向に沿って延びる辺とで画定される略長方形となるように形成されている。図示の実施形態において、複数のトレンチ11の各々は、平面視において、X軸方向に沿って延びる辺がY軸方向に沿って延びる辺よりも短くなるように形成されている。 The base material 10 has an upper surface 10a, a lower surface 10b on the opposite side of the upper surface 10a, a side surface 10c connecting the upper surface 10a and the lower surface 10b, and a wall portion 12 defining a trench 11 described later. In the embodiment of FIG. 1, the base material 10 has a substantially rectangular parallelepiped shape, and in the present specification, the four surfaces connecting the upper surface 10a and the lower surface 10b of the base material 10 are collectively referred to as a side surface 10c. A plurality of trenches 11 extending from the upper surface 10a of the base material 10 along the Z-axis direction are formed. Each of the plurality of trenches 11 is formed so as to have a predetermined depth in the Z-axis direction. In the present specification, the Z-axis direction may be referred to as the depth direction of the trench 11. As shown in FIG. 1, each of the plurality of trenches 11 has a substantially rectangular shape whose plan view shape is defined by a side extending along the X-axis direction and a side extending along the Y-axis direction. It is formed to be. In the illustrated embodiment, each of the plurality of trenches 11 is formed so that the side extending along the X-axis direction is shorter than the side extending along the Y-axis direction in a plan view.
 一実施形態において、複数のトレンチ11の各々は、単位面積あたりの高容量化を実現するために、高アスペクト比を有するように形成される。つまり、複数のトレンチ11の各々は、その幅(例えば、X軸方向の辺の長さ)に対する深さ(Z軸方向の寸法)の比が大きくなるように形成される。複数のトレンチ11の各々の幅(X軸方向における寸法)は例えば0.1μm~5μmとされ、その深さ(Z軸方向における寸法)は例えば1μm~100μmとされる。本明細書において具体的に示されるトレンチ11の寸法は例示に過ぎず、トレンチ11は任意の寸法をとることができる。また、トレンチ11の平面視における形状は長方形形状に限られず、トレンチ11は任意の形状をとることができる。一実施形態において、トレンチ11は、その深さ(Z軸方向における寸法)が30μmであり、その幅(X軸方向における寸法)が1.0μmとなるように構成される。 In one embodiment, each of the plurality of trenches 11 is formed to have a high aspect ratio in order to realize a high capacity per unit area. That is, each of the plurality of trenches 11 is formed so that the ratio of the depth (dimension in the Z-axis direction) to the width (for example, the length of the side in the X-axis direction) is large. The width of each of the plurality of trenches 11 (dimensions in the X-axis direction) is, for example, 0.1 μm to 5 μm, and the depth thereof (dimensions in the Z-axis direction) is, for example, 1 μm to 100 μm. The dimensions of the trench 11 specifically shown in the present specification are merely examples, and the trench 11 can take any dimension. Further, the shape of the trench 11 in a plan view is not limited to a rectangular shape, and the trench 11 can take any shape. In one embodiment, the trench 11 is configured such that its depth (dimensions in the Z-axis direction) is 30 μm and its width (dimensions in the X-axis direction) is 1.0 μm.
 トレンチ11は、例えばSi基板の表面にトレンチ11のパターンに対応する開口が形成されたマスクを形成した後、エッチングにより当該Si基板をエッチングすることで形成され得る。トレンチ11のエッチング加工は、ボッシュプロセスを用いた深掘りRIE(深掘り反応性エッチング)等の反応性イオンエッチング法により行われ得る。 The trench 11 can be formed, for example, by forming a mask having openings corresponding to the pattern of the trench 11 formed on the surface of the Si substrate and then etching the Si substrate by etching. The etching process of the trench 11 can be performed by a reactive ion etching method such as deep digging RIE (deep digging reactive etching) using a Bosch process.
 複数のトレンチ11のうち隣接するトレンチ11同士は壁部12によって隔てられている。言い換えると、壁部12は、基材10の一部であり、隣接するトレンチ11を互いから離隔させるように構成される。壁部12の表面である壁面13は、トレンチ11を画定している。壁面13は、上下方向(すなわち、Z軸方向)に沿って延びる側面13Aと、上面10aに沿った方向(すなわち、X軸方向又はY軸方向)に延びる底面13Bと、を含む。 Of the plurality of trenches 11, adjacent trenches 11 are separated from each other by a wall portion 12. In other words, the wall portion 12 is a part of the base material 10 and is configured to separate adjacent trenches 11 from each other. The wall surface 13, which is the surface of the wall portion 12, defines the trench 11. The wall surface 13 includes a side surface 13A extending along the vertical direction (that is, the Z-axis direction) and a bottom surface 13B extending in a direction along the upper surface 10a (that is, the X-axis direction or the Y-axis direction).
 続いて、MIM構造体20について説明する。前述のように、基材10には、MIM構造体20が設けられる。図示のように、MIM構造体20は、その一部がトレンチ11の各々に埋め込まれるように、基材10に設けられている。 Next, the MIM structure 20 will be described. As described above, the base material 10 is provided with the MIM structure 20. As shown, the MIM structure 20 is provided on the base material 10 so that a part thereof is embedded in each of the trenches 11.
 MIM構造体20は、基材10の上面10a及びトレンチ11に追従する形状を有するように構成される。MIM構造体20は、複数の導電層と、当該複数の導電層に挟まれた誘電体層とを有する。一実施形態では、MIM構造体20は、第1導電層と、第2導電層と、第1導電層と第2導電層とに挟まれた誘電体層とを有する。すなわち、MIM構造体20は、導電層と誘電体層とが交互に積層された積層体である。図示の実施形態におけるMIM構造体20は、下部電極層22(第2導電層)と、当該下部電極層22の上に設けられた誘電体層21と、当該誘電体層21の上に設けられた上部電極層23(第1導電層)と、を有する。本明細書においてMIM構造体20における上下方向に言及する場合には、下部電極及び上部電極という慣用されている名称と整合性をとるために、Z軸方向に沿う上下方向ではなく、基材10により近い側を「下」とし、基材10からより遠い側を「上」として説明がなされることがある。MIM構造体20は、2層以上のMIM層を含んでもよい。例えば、MIM構造体20が2層のMIM層を有する場合には、下部電極層22、誘電体層21、及び上部電極層23から構成される第1層目のMIM層の上に第2層目のMIM層が形成される。例えば、第2層目のMIM層は、上部電極層23の上に設けられた誘電体層と、この誘電体層の上に設けられた電極層と、を備えることができる。この場合、上部電極層23は、第1層目のMIM層の上側の電極層としての機能と、第2層目のMIM層の下側の電極層としての機能を兼ねる。 The MIM structure 20 is configured to have a shape that follows the upper surface 10a of the base material 10 and the trench 11. The MIM structure 20 has a plurality of conductive layers and a dielectric layer sandwiched between the plurality of conductive layers. In one embodiment, the MIM structure 20 has a first conductive layer, a second conductive layer, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer. That is, the MIM structure 20 is a laminated body in which conductive layers and dielectric layers are alternately laminated. The MIM structure 20 in the illustrated embodiment is provided on the lower electrode layer 22 (second conductive layer), the dielectric layer 21 provided on the lower electrode layer 22, and the dielectric layer 21. It also has an upper electrode layer 23 (first conductive layer). When referring to the vertical direction in the MIM structure 20 in the present specification, in order to be consistent with the commonly used names of lower electrode and upper electrode, the base material 10 is not used in the vertical direction along the Z-axis direction. The side closer to the base material 10 may be referred to as "lower", and the side farther from the base material 10 may be referred to as "upper". The MIM structure 20 may include two or more MIM layers. For example, when the MIM structure 20 has two MIM layers, a second layer is placed on the first MIM layer composed of the lower electrode layer 22, the dielectric layer 21, and the upper electrode layer 23. The MIM layer of the eye is formed. For example, the second MIM layer can include a dielectric layer provided on the upper electrode layer 23 and an electrode layer provided on the dielectric layer. In this case, the upper electrode layer 23 has both a function as an upper electrode layer of the first MIM layer and a function as a lower electrode layer of the second MIM layer.
 誘電体層21の材料として、BST(チタン酸バリウムストロンチウム)、BTO(チタン酸バリウム)、チタン酸ストロンチウム(STO)、ジルコニア(ZrO2)、アルミナ(Al23)、酸化ハフニウム(HfO2)、酸化チタン(TiO2)、及びこれら以外の誘電体材料を用いることができる。誘電体層21の材料は、本明細書で明示的に説明されたものには限定されない。 As the material of the dielectric layer 21, BST (barium titanate), BTO (barium titanate), strontium titanate (STO), zirconia (ZrO 2 ), alumina (Al 2 O 3 ), hafnium oxide (HfO 2 ) , Titanium oxide (TiO 2 ), and other dielectric materials can be used. The material of the dielectric layer 21 is not limited to those explicitly described herein.
 誘電体層21は、例えば、ALD(原子層堆積)法、スパッタ法、CVD法、蒸着法、めっき法、又はこれら以外の公知の方法により形成される。誘電体層21は、その膜厚が例えば1nm~500nmとなるように形成される。一実施形態において、誘電体層21の膜厚は、100nmとされる。 The dielectric layer 21 is formed by, for example, an ALD (atomic layer deposition) method, a sputtering method, a CVD method, a vapor deposition method, a plating method, or a known method other than these. The dielectric layer 21 is formed so that its film thickness is, for example, 1 nm to 500 nm. In one embodiment, the film thickness of the dielectric layer 21 is 100 nm.
 下部電極22及び上部電極23の材料として、ニッケル(Ni)、銅(Cu)、パラジウム(Pd)、白金(Pt)、銀(Ag)、金(Au)、ルテニウム(Ru)、タングステン(W)、モリブデン(Mo)、チタン(Ti)、導電性シリコン、これらの金属元素の一又は複数を含む合金材料、及び前記金属元素の化合物、もしくはこれら以外の金属材料を用いることができる。一実施形態においては、下部電極層22及び上部電極層23の材料として、白金(Pt)が用いられる。下部電極層22及び上部電極層23の材料として窒化チタン(TiN)が用いられてもよい。下部電極層22及び上部電極層23の材料は、本明細書で明示的に説明されたものには限定されない。 Materials for the lower electrode 22 and the upper electrode 23 are nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), ruthenium (Ru), and tungsten (W). , Molybdenum (Mo), titanium (Ti), conductive silicon, alloy materials containing one or more of these metal elements, compounds of the metal elements, or metal materials other than these. In one embodiment, platinum (Pt) is used as the material for the lower electrode layer 22 and the upper electrode layer 23. Titanium nitride (TiN) may be used as a material for the lower electrode layer 22 and the upper electrode layer 23. The materials of the lower electrode layer 22 and the upper electrode layer 23 are not limited to those explicitly described herein.
 下部電極層22及び上部電極層23は、例えば、ALD(原子層堆積)法、スパッタ法、蒸着法、めっき法、又はこれら以外の公知の方法により形成される。一実施形態において、下部電極層22は、その膜厚が例えば1nm~500nmとなるように形成される。一実施形態において、上部電極23は、その膜厚が例えば1nm~500nmとなるように形成される。下部電極層22及び上部電極層23の詳細な構造については、後述する。 The lower electrode layer 22 and the upper electrode layer 23 are formed by, for example, an ALD (atomic layer deposition) method, a sputtering method, a vapor deposition method, a plating method, or a known method other than these. In one embodiment, the lower electrode layer 22 is formed so that its film thickness is, for example, 1 nm to 500 nm. In one embodiment, the upper electrode 23 is formed so that its film thickness is, for example, 1 nm to 500 nm. The detailed structure of the lower electrode layer 22 and the upper electrode layer 23 will be described later.
 続いて、保護層40について説明する。保護層40は、外部環境からMIM構造体20を保護するために、MIM構造体20及び基材10を覆うように設けられる。保護層40は、例えば、外部から受ける衝撃等の機械的ダメージからMIM構造体20を保護するように設けられる。保護層40の材料として、ポリイミド等の樹脂材料、酸化シリコン(SiO2)、窒化シリコン(SiN)、酸窒化シリコン(SiON)、及びこれら以外の絶縁材料を用いることができる。保護層40は、例えば、スピンコート法により感光性ポリイミドを塗布し、この塗布されたポリイミドを露光、現像、及びキュアすることにより形成される。保護層40は、その膜厚が例えば200nm~5000nmとなるように形成される。一実施形態において、保護層40の膜厚は3000nmとされる。保護層40の材料及び膜厚は、本明細書で明示的に説明されたものには限定されない。 Subsequently, the protective layer 40 will be described. The protective layer 40 is provided so as to cover the MIM structure 20 and the base material 10 in order to protect the MIM structure 20 from the external environment. The protective layer 40 is provided so as to protect the MIM structure 20 from mechanical damage such as an impact received from the outside, for example. As the material of the protective layer 40, a resin material such as polyimide, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and other insulating materials can be used. The protective layer 40 is formed by, for example, applying a photosensitive polyimide by a spin coating method, and exposing, developing, and curing the applied polyimide. The protective layer 40 is formed so that its film thickness is, for example, 200 nm to 5000 nm. In one embodiment, the film thickness of the protective layer 40 is 3000 nm. The material and film thickness of the protective layer 40 are not limited to those expressly described herein.
 保護層40とMIM構造体20(又は基材10)との間には、不図示のバリア層が設けられていてもよい。バリア層は、トレンチキャパシタ1の耐候性を向上させるために、主にMIM構造体20の上に設けられる。一実施形態において、バリア層は、保護層40から放出される水分や大気中の水分がMIM構造体20に到達しないように、MIM構造体20と保護層40との間に設けられる。バリア層は、水素ガスバリア性に優れた薄膜であってもよい。バリア層の材料として、アルミナ(Al23)、酸化シリコン(SiO2)、酸窒化シリコン(SiON)、ジルコニア(ZrO2)、及びこれら以外の絶縁材料を用いることができる。バリア層は、例えば、スパッタ法、CVD法、又はこれら以外の公知の方法により形成される。バリア層は、その膜厚が例えば5nm~500nmとなるように形成される。一実施形態において、バリア層の膜厚は50nmとされる。バリア層の材料及び膜厚は、本明細書で明示的に説明されたものには限定されない。 A barrier layer (not shown) may be provided between the protective layer 40 and the MIM structure 20 (or the base material 10). The barrier layer is mainly provided on the MIM structure 20 in order to improve the weather resistance of the trench capacitor 1. In one embodiment, the barrier layer is provided between the MIM structure 20 and the protective layer 40 so that the moisture released from the protective layer 40 and the moisture in the atmosphere do not reach the MIM structure 20. The barrier layer may be a thin film having excellent hydrogen gas barrier properties. As the material of the barrier layer, alumina (Al 2 O 3 ), silicon oxide (SiO 2 ), silicon oxynitride (SiON), zirconia (ZrO 2 ), and other insulating materials can be used. The barrier layer is formed by, for example, a sputtering method, a CVD method, or a known method other than these. The barrier layer is formed so that its film thickness is, for example, 5 nm to 500 nm. In one embodiment, the film thickness of the barrier layer is 50 nm. The material and film thickness of the barrier layer are not limited to those expressly described herein.
 続いて、外部電極2及び外部電極3について説明する。外部電極2及び外部電極3は、保護層40の上側に、Y軸方向において互いから離間するように設けられる。外部電極2及び外部電極3は、保護層40の外側に金属材料を含む導体ペーストを塗布することにより形成される。外部電極2及び外部電極3の材料として、銅(Cu)、ニッケル(Ni)、スズ(Sn)、パラジウム(Pd)、白金(Pt)、銀(Ag)、金(Au)、もしくはこれら以外の金属材料、又は、これらの金属元素の一又は複数を含む合金材料を用いることができる。外部電極2及び外部電極3には、必要に応じて、半田バリア層及び半田漏れ層の少なくとも一方が形成されてもよい。 Next, the external electrode 2 and the external electrode 3 will be described. The external electrode 2 and the external electrode 3 are provided on the upper side of the protective layer 40 so as to be separated from each other in the Y-axis direction. The external electrode 2 and the external electrode 3 are formed by applying a conductor paste containing a metal material to the outside of the protective layer 40. Materials of the external electrode 2 and the external electrode 3 include copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or other materials. A metal material or an alloy material containing one or more of these metal elements can be used. At least one of a solder barrier layer and a solder leakage layer may be formed on the external electrode 2 and the external electrode 3, if necessary.
 保護層40のY軸負方向の端の近くには溝41が設けられており、Y軸正方向の端の近くには溝42が設けられている。溝41及び溝42はいずれも、X軸方向に沿って延伸すると共に保護層40をZ軸方向に貫通する用に設けられている。溝41には引出電極2aが設けられ、溝42には引出電極3aが設けられている。 A groove 41 is provided near the end of the protective layer 40 in the negative direction of the Y axis, and a groove 42 is provided near the end of the protective layer 40 in the positive direction of the Y axis. Both the groove 41 and the groove 42 are provided so as to extend along the X-axis direction and penetrate the protective layer 40 in the Z-axis direction. The groove 41 is provided with an extraction electrode 2a, and the groove 42 is provided with an extraction electrode 3a.
 引出電極2aの上端は外部電極2に接続され、引出電極2aの下端はMIM構造体20の下部電極層22に接続される。引出電極3aの上端は外部電極3に接続され、引出電極3aの下端はMIM構造体20の上部電極23に接続される。 The upper end of the extraction electrode 2a is connected to the external electrode 2, and the lower end of the extraction electrode 2a is connected to the lower electrode layer 22 of the MIM structure 20. The upper end of the extraction electrode 3a is connected to the external electrode 3, and the lower end of the extraction electrode 3a is connected to the upper electrode 23 of the MIM structure 20.
 引出電極2a、3aの材料として、銅(Cu)、ニッケル(Ni)、スズ(Sn)、パラジウム(Pd)、白金(Pt)、銀(Ag)、金(Au)、もしくはこれら以外の金属材料、又は、これらの金属元素の一又は複数を含む合金材料を用いることができる。引出電極2a、3aは、蒸着法、スパッタ法、メッキ法、又はこれら以外の公知の方法により形成される。 As the material of the extraction electrodes 2a and 3a, copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or a metal material other than these. , Or an alloy material containing one or more of these metal elements can be used. The extraction electrodes 2a and 3a are formed by a vapor deposition method, a sputtering method, a plating method, or a known method other than these.
 次に、図3を参照して、MIM構造体20の下部電極層22及び上部電極層23について詳細に説明する。図3に示されるように、下部電極層22及び上部電極層23のそれぞれは、トレンチ11の外に位置すると共に上面10aに沿って延びる第1部分22R1,23R1と、トレンチ11内に位置すると共にトレンチ11の壁面13に沿って延びる第2部分22R2,23R2と、を有している。上部電極層23の第1部分23R1の厚さ23T1は、上部電極23の第2部分23R2の厚さ23T2より大きい。本明細書において、第1部分22R1,23R1の厚さ22T1,23T1とは、それぞれ、Z軸方向における下部電極層22又は上部電極層23の寸法をいう。第2部分22R2,23R2の厚さ22T2,23T2とは、それぞれ、壁部12の壁面13に対して垂直な方向における下部電極層22又は上部電極層23の寸法をいう。具体的に、第2部分22R2,23R2のうちトレンチ11の底面13Bに沿った部分の厚さは、Z軸方向の下部電極層22又は上部電極層23の寸法をいい、第2部分22R2,23R2のうちトレンチ11の側面13Aに沿った部分の厚さは、X軸又はY軸方向の下部電極層22又は上部電極層23の寸法をいう。トレンチ11内が埋まって上部電極層23同士の間に隙間がない場合(すなわち、第2部23R2のうち、側面13Aに沿った部分と底面13Bに沿った部分とを明確に区別できない場合)には、X軸方向又はY軸方向における誘電体層21同士の間の間隔の半分を第2部分23R2の厚さ23T2とする。上部電極層23の第1部分23R1の厚さ23T1は、例えば、第2部分の厚さ23T2の2倍以上且つ50倍以とすることができる。特に、上部電極層23の第1部分23R1の厚さ23T1は、上部電極層23の第2部分23R2の厚さ23T2の2.5倍以上であることが好ましい。一例として、上部電極層23の第1部分23R1の厚さ23T1は200nmであり、上部電極層23の第2部分23R2の厚さ23T2は50nmである。 Next, the lower electrode layer 22 and the upper electrode layer 23 of the MIM structure 20 will be described in detail with reference to FIG. As shown in FIG. 3, each of the lower electrode layer 22 and the upper electrode layer 23 is located outside the trench 11 and is located inside the trench 11 as well as the first portions 22R1, 23R1 extending along the upper surface 10a. It has a second portion 22R2, 23R2 extending along the wall surface 13 of the trench 11. The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is larger than the thickness 23T2 of the second portion 23R2 of the upper electrode 23. In the present specification, the thicknesses 22T1, 23T1 of the first portion 22R1, 23R1 refer to the dimensions of the lower electrode layer 22 or the upper electrode layer 23 in the Z-axis direction, respectively. The thicknesses 22T2 and 23T2 of the second portions 22R2 and 23R2 refer to the dimensions of the lower electrode layer 22 or the upper electrode layer 23 in the direction perpendicular to the wall surface 13 of the wall portion 12, respectively. Specifically, the thickness of the portion of the second portion 22R2, 23R2 along the bottom surface 13B of the trench 11 refers to the dimension of the lower electrode layer 22 or the upper electrode layer 23 in the Z-axis direction, and the second portion 22R2, 23R2. The thickness of the portion along the side surface 13A of the trench 11 refers to the dimension of the lower electrode layer 22 or the upper electrode layer 23 in the X-axis or Y-axis direction. When the inside of the trench 11 is filled and there is no gap between the upper electrode layers 23 (that is, the portion of the second portion 23R2 along the side surface 13A and the portion along the bottom surface 13B cannot be clearly distinguished). The half of the distance between the dielectric layers 21 in the X-axis direction or the Y-axis direction is the thickness 23T2 of the second portion 23R2. The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 can be, for example, twice or more and 50 times or more the thickness of the second portion 23T2. In particular, the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is preferably 2.5 times or more the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23. As an example, the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is 200 nm, and the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23 is 50 nm.
 上部電極層23の第1部分23R1は、第1層23Aと、第1層23Aの上に設けられた第2層23Bと、を含む多層構造を有する。上部電極層23の第1部分23R1を構成する層の数は特に限定されず、第1部分23R1は3層以上の多層構造を有していてもよい。図示の実施形態では、上部電極層23の第1部分23R1は第1層23A及び第2層23Bの2層によって構成され、第2部分23R2は第1層23Aのみによって構成されている。上部電極層23の第1層23Aは誘電体層21と接し、上部電極層23の第2層23Bは保護層40と接触する。第1層23Aの厚さは、第2部分23R2の厚さT2と略同一である。第1層23Aの厚さは、例えば50nmであり、第2層23Bの厚さは、例えば150nmである。第1層23Aと第2層23Bとは、互いに同一の材料によって構成されてもよいし、互いに異なる材料によって構成されてもよい。図示の実施形態では、第1層23Aと第2層23Bとは互いに異なる材料によって構成され、第2層23Bを構成する材料の導電率は、第1層23Aを構成する材料の導電率より高くなっている。第1層23Aと第2層23Bとは互いに異なる材料によって構成される場合、第1層23Aと第2層23Bとの密着性を向上させるために、第1層23Aと第2層23Bとの間に密着層を設けてもよい。密着層を構成する材料としては、例えばTi、又はTiN、Ta、TaN等が挙げられる。一例として、第1層23AはPtによって構成され、第2層23BはCuによって構成される。この場合、第1層23Aと第2層23Bとの間の密着層は、Tiによって構成される。 The first portion 23R1 of the upper electrode layer 23 has a multilayer structure including a first layer 23A and a second layer 23B provided on the first layer 23A. The number of layers constituting the first portion 23R1 of the upper electrode layer 23 is not particularly limited, and the first portion 23R1 may have a multilayer structure of three or more layers. In the illustrated embodiment, the first portion 23R1 of the upper electrode layer 23 is composed of two layers, the first layer 23A and the second layer 23B, and the second portion 23R2 is composed of only the first layer 23A. The first layer 23A of the upper electrode layer 23 is in contact with the dielectric layer 21, and the second layer 23B of the upper electrode layer 23 is in contact with the protective layer 40. The thickness of the first layer 23A is substantially the same as the thickness T2 of the second portion 23R2. The thickness of the first layer 23A is, for example, 50 nm, and the thickness of the second layer 23B is, for example, 150 nm. The first layer 23A and the second layer 23B may be made of the same material as each other, or may be made of different materials from each other. In the illustrated embodiment, the first layer 23A and the second layer 23B are made of different materials, and the conductivity of the material constituting the second layer 23B is higher than the conductivity of the material constituting the first layer 23A. It has become. When the first layer 23A and the second layer 23B are made of different materials, the first layer 23A and the second layer 23B are combined in order to improve the adhesion between the first layer 23A and the second layer 23B. An adhesion layer may be provided between them. Examples of the material constituting the adhesion layer include Ti, TiN, Ta, TaN and the like. As an example, the first layer 23A is composed of Pt and the second layer 23B is composed of Cu. In this case, the adhesion layer between the first layer 23A and the second layer 23B is composed of Ti.
 下部電極層22の第1部分22R1の厚さと、当該下部電極層22の第2部分22R2の厚さとは、略同一である。図示の実施形態では、下部電極層22の第1部分22R1は多層構造を有しておらず、1層のみから構成されている。上部電極層23の第1部分23R1の厚さ23T1は、下部電極層22の第1部分22R1の厚さ22T1より大きくなっている。一例として、下部電極層22の厚さは、50nmである。下部電極層22及び上部電極層23の膜厚は、本明細書で明示的に説明されたものに限定されない。 The thickness of the first portion 22R1 of the lower electrode layer 22 and the thickness of the second portion 22R2 of the lower electrode layer 22 are substantially the same. In the illustrated embodiment, the first portion 22R1 of the lower electrode layer 22 does not have a multi-layer structure and is composed of only one layer. The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is larger than the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22. As an example, the thickness of the lower electrode layer 22 is 50 nm. The film thicknesses of the lower electrode layer 22 and the upper electrode layer 23 are not limited to those explicitly described herein.
 次に、トレンチキャパシタ1の製造方法について説明する。まず、上面10a、上面10aとは反対側の下面、及び上下方向に沿って上面10aから延びるトレンチ11を有する基材を準備する。具体的には、基材10となるウェハを準備し、トレンチ11のパターンに対応したマスクをウェハの上面に形成する。次に、ウェハをエッチングすることにより、複数のトレンチ11を形成する。これにより、壁部12及びトレンチ11を画定する壁面13が形成される。ウェハのエッチングは、例えばボッシュプロセス等を用いたドライエッチングによってなされる。 Next, the manufacturing method of the trench capacitor 1 will be described. First, a base material having an upper surface 10a, a lower surface opposite to the upper surface 10a, and a trench 11 extending from the upper surface 10a along the vertical direction is prepared. Specifically, a wafer to be the base material 10 is prepared, and a mask corresponding to the pattern of the trench 11 is formed on the upper surface of the wafer. Next, the wafer is etched to form a plurality of trenches 11. As a result, the wall surface 13 that defines the wall portion 12 and the trench 11 is formed. Wafer etching is performed by dry etching using, for example, a Bosch process.
 次に、ウェハからマスクを除去し、ウェハの上面及び壁部12に沿ってMIM構造体20を形成する。MIM構造体20を形成する工程は、導電層を形成する工程と、誘電体層を形成する工程とを含む。MIM構造体20を形成する工程では、まず、下部電極層22を形成する。下部電極層22は、例えばPtによって形成される。次に、下部電極層22の上に誘電体層21を形成する。誘電体層21は、例えばジルコニアから形成される。下部電極層22及び誘電体層21は、例えばALD法又はCVD法等の化学気相成長法によって形成され得る。次に、誘電体層21の上に、上部電極層23を形成する。上部電極層23を形成する工程は、化学気相成長を行う工程と、物理気相成長を行う工程と、を含む。上部電極層23を行う際には、まずALD法又はCVD法等の化学気相成長を行うことにより第1層23Aを形成する。次に、スパッタ法又は真空蒸着法等の物理気相成長を行うことにより、第2層23Bを形成する。物理気相成長法では、トレンチ11内に第2層23Bの材料が供給されにくいので、第2層23Bはトレンチ11内に成膜されにくく、ウェハの上面に成膜される。このため、基材10の上面10aに沿った第1部分23R1の厚さは、トレンチ11の壁面13に沿って延びる第2部分23R2の厚さよりも大きくなる。以上の工程により、MIM構造体20が形成される。 Next, the mask is removed from the wafer to form the MIM structure 20 along the upper surface and the wall portion 12 of the wafer. The step of forming the MIM structure 20 includes a step of forming a conductive layer and a step of forming a dielectric layer. In the step of forming the MIM structure 20, first, the lower electrode layer 22 is formed. The lower electrode layer 22 is formed of, for example, Pt. Next, the dielectric layer 21 is formed on the lower electrode layer 22. The dielectric layer 21 is formed from, for example, zirconia. The lower electrode layer 22 and the dielectric layer 21 can be formed by a chemical vapor deposition method such as an ALD method or a CVD method. Next, the upper electrode layer 23 is formed on the dielectric layer 21. The step of forming the upper electrode layer 23 includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition. When the upper electrode layer 23 is formed, the first layer 23A is first formed by performing chemical vapor deposition such as an ALD method or a CVD method. Next, the second layer 23B is formed by performing physical vapor deposition such as a sputtering method or a vacuum vapor deposition method. In the physical vapor deposition method, since the material of the second layer 23B is difficult to be supplied into the trench 11, the second layer 23B is difficult to be formed in the trench 11 and is formed on the upper surface of the wafer. Therefore, the thickness of the first portion 23R1 along the upper surface 10a of the base material 10 is larger than the thickness of the second portion 23R2 extending along the wall surface 13 of the trench 11. The MIM structure 20 is formed by the above steps.
 次に、MIM構造体20の上に保護層40を形成する。このとき、保護層40のうちMIM構造体20の上側に設けられている部分のY軸方向の両端の各々の近くに、それぞれ溝を設ける。次に、めっき法などにより、溝の内部に引出電極2a,3aを形成すると共に、保護層40の表面に外部電極2及び外部電極3を形成する。最後に、ウェハを個片化する。以上の工程により、複数のトレンチキャパシタ1が得られる。 Next, the protective layer 40 is formed on the MIM structure 20. At this time, grooves are provided near both ends in the Y-axis direction of the portion of the protective layer 40 provided on the upper side of the MIM structure 20. Next, the extraction electrodes 2a and 3a are formed inside the groove by a plating method or the like, and the external electrode 2 and the external electrode 3 are formed on the surface of the protective layer 40. Finally, the wafer is fragmented. By the above steps, a plurality of trench capacitors 1 can be obtained.
 次に、トレンチキャパシタ1の作用効果について説明する。以上説明したように、トレンチキャパシタ1の下部電極層22及び上部電極層23(すなわち、複数の導電層)のそれぞれは、トレンチ11の外に位置すると共に上面10aに沿って延びる第1部分22R1,23R1と、トレンチ11内に位置すると共にトレンチ11の壁面13に沿って延びる第2部分22R2,23R1と、を有し、上部電極層23の第1部分23R1の厚さ23T1は、当該上部電極層23の第2部分23R2の厚さ23T2より大きい。 Next, the action and effect of the trench capacitor 1 will be described. As described above, each of the lower electrode layer 22 and the upper electrode layer 23 (that is, the plurality of conductive layers) of the trench capacitor 1 is located outside the trench 11 and extends along the upper surface 10a. It has a 23R1 and a second portion 22R2, 23R1 that is located in the trench 11 and extends along the wall surface 13 of the trench 11, and the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is the upper electrode layer. The thickness of the second portion 23R2 of 23 is larger than the thickness 23T2.
 一般的なトレンチキャパシタにおいては、単位面積当たりの発生容量を向上させるためにトレンチパターンの微細化が求められている。しかしながら、トレンチパターンを微細化すると、トレンチ11内においては基材10の表面10aに沿った方向(すなわち、X軸方向及びY軸方向)における寸法の制限が厳しくなるので、MIM構造体20の下部電極層及び上部電極層の厚さを薄くする必要がある。その結果、一般的なキャパシタでは電流経路の断面積が小さくなり、等価直列抵抗(ESR)が大きくなりやすいという問題がある。 In a general trench capacitor, miniaturization of the trench pattern is required in order to improve the generated capacity per unit area. However, when the trench pattern is miniaturized, the dimensional restrictions in the direction along the surface 10a of the base material 10 (that is, the X-axis direction and the Y-axis direction) become strict in the trench 11, so that the lower part of the MIM structure 20 It is necessary to reduce the thickness of the electrode layer and the upper electrode layer. As a result, in a general capacitor, there is a problem that the cross-sectional area of the current path becomes small and the equivalent series resistance (ESR) tends to be large.
 本発明者は、トレンチキャパシタのMIM構造体の導電層(すなわち、下部電極層及び上部電極層)においては、トレンチの内部(すなわち、第2部分22R2,23R2)に流れる電流量が少なく、基板の表面に沿った部分(すなわち、第1部分22R1,23R1)に流れる電流量が多いことを見出した。そこで、トレンチキャパシタ1では、下部電極層22及び上部電極層23のうち、少なくとも一の導電層(図示の実施形態では、上部電極層23)の第1部分23R1の厚さ23T1を、当該一の導電層(すなわち、上部電極層23)の第2部分23R2の厚さ23T2より大きくしている。このように、多くの電流が流れる第1部分23R1の厚さ23T1が大きくなっていることにより、等価直列抵抗(ESR)への影響が大きい部分において電流経路の断面積を大きくすることができる。したがって、等価直列抵抗の低下を図ることができる。 In the conductive layer (that is, the lower electrode layer and the upper electrode layer) of the MIM structure of the trench capacitor, the present inventor has a small amount of current flowing inside the trench (that is, the second portion 22R2, 23R2), and the substrate has a small amount of current. It has been found that the amount of current flowing in the portion along the surface (that is, the first portion 22R1, 23R1) is large. Therefore, in the trench capacitor 1, the thickness 23T1 of the first portion 23R1 of at least one conductive layer (upper electrode layer 23 in the illustrated embodiment) among the lower electrode layer 22 and the upper electrode layer 23 is set to the one. The thickness of the second portion 23R2 of the conductive layer (that is, the upper electrode layer 23) is made larger than the thickness 23T2. As described above, since the thickness 23T1 of the first portion 23R1 through which a large amount of current flows is increased, the cross-sectional area of the current path can be increased in the portion having a large influence on the equivalent series resistance (ESR). Therefore, the equivalent series resistance can be reduced.
 また、第1部分23R1の厚さ23T1のみが相対的に大きくなっていることにより、上面10aに沿った方向におけるトレンチ11の寸法を大きくすることなく電流経路の断面積を大きくすることができる。したがって、単位面積当たりの発生容量を保ちつつ、等価直列抵抗の低下を図ることができる。 Further, since only the thickness 23T1 of the first portion 23R1 is relatively large, the cross-sectional area of the current path can be increased without increasing the size of the trench 11 in the direction along the upper surface 10a. Therefore, it is possible to reduce the equivalent series resistance while maintaining the generated capacity per unit area.
 上部電極層23の第1部分23R1の厚さ23T1は、上部電極層23の第2部分23R2の厚さ23T2の2倍以上且つ50倍以下である。第1部分23R1の厚さ23T1を第2部分23R2の厚さ23T2の50倍以下とすることにより、効果的に等価直列抵抗の低下を図ることができる。また、第1部分23R1の厚さ23T1を第2部分23R2の厚さ23T2の50倍以下とすることにより、製造過程で物理気相成長法によって第2層23Bを形成する工程においてトレンチ11が塞がれてしまうことを抑制できる。 The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 is twice or more and 50 times or less the thickness of the second portion 23R2 of the upper electrode layer 23. By setting the thickness 23T1 of the first portion 23R1 to 50 times or less the thickness 23T2 of the second portion 23R2, the equivalent series resistance can be effectively reduced. Further, by making the thickness 23T1 of the first portion 23R1 50 times or less the thickness 23T2 of the second portion 23R2, the trench 11 is blocked in the step of forming the second layer 23B by the physical vapor deposition method in the manufacturing process. It is possible to prevent it from coming off.
 上部電極層23の第1部分23R1は、第1層23Aと、第1層23Aの上に設けられた第2層23Bと、を含む多層構造を有している。これにより、第1層23A及び第2層23Bを互いに異なる材料によって構成することができる。また、第1層23Aと第2層23Bとを互いに異なる方法によって形成することができるので、相対的に厚さが大きい第2層23Bを成膜レートの高い方法で形成することができる。 The first portion 23R1 of the upper electrode layer 23 has a multilayer structure including a first layer 23A and a second layer 23B provided on the first layer 23A. As a result, the first layer 23A and the second layer 23B can be made of different materials. Further, since the first layer 23A and the second layer 23B can be formed by different methods, the second layer 23B having a relatively large thickness can be formed by a method having a high film forming rate.
 トレンチキャパシタ1では、第2層23Bを構成する材料の導電率は、第1層23Aを構成する材料の導電率より高くなっている。これにより、トレンチキャパシタ1の等価直列抵抗を更に低減することができる。 In the trench capacitor 1, the conductivity of the material constituting the second layer 23B is higher than the conductivity of the material constituting the first layer 23A. Thereby, the equivalent series resistance of the trench capacitor 1 can be further reduced.
 また、トレンチキャパシタ1の製造方法において、上部電極23を形成する工程は、化学気相成長を行う工程と、物理気相成長を行う工程と、を含む。化学気相成長を行う工程では、基材10の上面10a及びトレンチ11の壁面に沿って上部電極23の第1層23Aが形成される。一方、物理気相成長を行う工程では、トレンチ11内に第2層23Bの材料が供給されにくいので、基材10の上面10aに第2層23Bが形成される。これにより、トレンチ11の外に位置すると共に上面10aに沿って延びる上部電極層23の第1部分23R1の厚さ23T1は、トレンチ11内に位置すると共にトレンチ11の壁面13に沿って延びる上部電極層23の第2部分23R2の厚さ23T2より大きくすることができる。したがって、上面10aに沿った方向(すなわち、上下方向に直交する方向)におけるトレンチ11の寸法を拡大することなく電流経路の断面積を大きくすることができ、単位面積当たりの発生容量を保ちつつ、等価直列抵抗の低下を図ることができる。 Further, in the method for manufacturing the trench capacitor 1, the step of forming the upper electrode 23 includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition. In the step of performing chemical vapor deposition, the first layer 23A of the upper electrode 23 is formed along the upper surface 10a of the base material 10 and the wall surface of the trench 11. On the other hand, in the step of performing physical vapor deposition, it is difficult to supply the material of the second layer 23B into the trench 11, so that the second layer 23B is formed on the upper surface 10a of the base material 10. As a result, the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 located outside the trench 11 and extending along the upper surface 10a is located inside the trench 11 and extends along the wall surface 13 of the trench 11. The thickness of the second portion 23R2 of the layer 23 can be made larger than the thickness 23T2. Therefore, the cross-sectional area of the current path can be increased without enlarging the size of the trench 11 in the direction along the upper surface 10a (that is, the direction orthogonal to the vertical direction), and the generated capacity per unit area can be maintained. The equivalent series resistance can be reduced.
 次に、図4を参照して、他の実施形態に係るトレンチキャパシタ100について説明する。図4に示されるように、他の実施形態に係るトレンチキャパシタ100は、トレンチキャパシタ1と同様に、上面10aから延びるトレンチ11を有する基材10と、複数の導電層(すなわち、上部電極層23及び下部電極22)と、複数の導電層に挟まれた誘電体層21とを有し、上面10a及びトレンチ11を画定する壁面13に沿って設けられたMIM構造体20と、を備えている。トレンチキャパシタ100がトレンチキャパシタ1と相違する点は、上部電極層23ではなく、下部電極層22の第1部分22R1の厚さ22T1が、当該下部電極層22の第2部分22R2の厚さ22T2より大きくなっている点である。トレンチキャパシタ100の下部電極層22の第1部分22R1は多層構造を有しており、第1層22A及び第2層22Bを含んでいる。下部電極層22の第1部分22R1の厚さ22T1は、下部電極層22の第2部分22R2の厚さ22T2の2倍以上50倍以下の範囲内に設定される。特に、第1部分22R1の厚さ22T1は、第2部分22R2の厚さ22T2の2.5倍以上であることが好ましい。一例として、第1部分22R1の厚さ22T1は200nm、第2部分22R2の厚さ22T2は50nmである。トレンチキャパシタ100の上部電極層23の第1部分23R1の厚さ23T1と、上部電極層23の第2部分23R2の厚さ23T1とは、略同一である。 Next, the trench capacitor 100 according to another embodiment will be described with reference to FIG. As shown in FIG. 4, the trench capacitor 100 according to another embodiment has a base material 10 having a trench 11 extending from the upper surface 10a and a plurality of conductive layers (that is, an upper electrode layer 23), similarly to the trench capacitor 1. And a lower electrode 22), and a MIM structure 20 having a dielectric layer 21 sandwiched between a plurality of conductive layers and provided along a wall surface 13 defining an upper surface 10a and a trench 11. .. The difference between the trench capacitor 100 and the trench capacitor 1 is that the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 is larger than the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22 instead of the upper electrode layer 23. It is a point that is getting bigger. The first portion 22R1 of the lower electrode layer 22 of the trench capacitor 100 has a multilayer structure, and includes the first layer 22A and the second layer 22B. The thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 is set within a range of twice or more and 50 times or less the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22. In particular, the thickness 22T1 of the first portion 22R1 is preferably 2.5 times or more the thickness 22T2 of the second portion 22R2. As an example, the thickness 22T1 of the first portion 22R1 is 200 nm, and the thickness 22T2 of the second portion 22R2 is 50 nm. The thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 of the trench capacitor 100 and the thickness 23T1 of the second portion 23R2 of the upper electrode layer 23 are substantially the same.
 トレンチキャパシタ100は、上記で説明されたトレンチキャパシタ1の製造方法と略同様の方法によって製造され得るが、下部電極層22を形成する工程において、化学気相成長法によって下部電極層22の第1層22Aを形成した後、物理気相成長法によって下部電極層22の第2層22Bを形成する点で異なる。上部電極層23は、ALD法又はCVD法等の化学気相成長法によって形成される。 The trench capacitor 100 can be manufactured by substantially the same method as the method for manufacturing the trench capacitor 1 described above, but in the step of forming the lower electrode layer 22, the first of the lower electrode layer 22 is produced by the chemical vapor deposition method. The difference is that after the layer 22A is formed, the second layer 22B of the lower electrode layer 22 is formed by the physical vapor deposition method. The upper electrode layer 23 is formed by a chemical vapor deposition method such as an ALD method or a CVD method.
 上記のトレンチキャパシタ100においては、下部電極層22の第1部分22R1の厚さ22T1が当該下部電極層22の第2部分22R2の厚さ22T2よりも厚くなっている。したがって、トレンチキャパシタ1と同様の理由により、単位面積当たりの発生容量を保ちつつ、等価直列抵抗の低下を図ることができる。 In the trench capacitor 100, the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 is thicker than the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22. Therefore, for the same reason as that of the trench capacitor 1, it is possible to reduce the equivalent series resistance while maintaining the generated capacity per unit area.
 次に、図5を参照して、他の実施形態に係るトレンチキャパシタ200について説明する。図5に示されるように、トレンチキャパシタ200は、トレンチキャパシタ1と同様に、上面10aから延びるトレンチ11を有する基材10と、複数の導電層(すなわち、上部電極層23及び下部電極22)と、複数の導電層に挟まれた誘電体層21とを有し、上面10a及びトレンチ11を画定する壁面に沿って設けられたMIM構造体20と、を備えている。トレンチキャパシタ200がトレンチキャパシタ1と相違する点は、上部電極層23及び下部電極層22の両方において、第1部分22R1,23R1の厚さ22T1,23T1が第2部分22R2,23R2の厚さ22T2,23T2より大きくなっている点である。トレンチキャパシタ200の下部電極層22の第1部分22R1は多層構造を有しており、第1層22A及び第2層22Bを含んでいる。同様に、上部電極層23の第1部分23R1も多層構造を有しており、第1層23A及び第2層23Bを含んでいる。下部電極層22及び上部電極層23の第1部分22R1,23R1の厚さ22T1,23T1は、第2部分22R2,23R2の厚さ22T2,23T2の2倍以上50倍以下の範囲内に設定される。図5に示される実施形態では、下部電極層22の第1部分22R1の厚さ22T1と上部電極層23の第1部分23R1の厚さ23T1とは略同一であるが、下部電極層22の第1部分22R1の厚さ22T1と上部電極層23の第1部分23R1の厚さ23T1とは互いに異なっていてもよい。また、下部電極層22の第2部分22R2の厚さ22T2と上部電極層23の第2部分23R2の厚さ23T2とは略同一であるが、下部電極層22の第2部分22R2の厚さ22T2と上部電極層23の第2部分23R2の厚さ23T2とは互いに異なっていてもよい。 Next, the trench capacitor 200 according to another embodiment will be described with reference to FIG. As shown in FIG. 5, the trench capacitor 200 includes a base material 10 having a trench 11 extending from the upper surface 10a and a plurality of conductive layers (that is, an upper electrode layer 23 and a lower electrode 22), similarly to the trench capacitor 1. A MIM structure 20 having a dielectric layer 21 sandwiched between a plurality of conductive layers and provided along a wall surface defining an upper surface 10a and a trench 11 is provided. The difference between the trench capacitor 200 and the trench capacitor 1 is that in both the upper electrode layer 23 and the lower electrode layer 22, the thickness 22T1,23T1 of the first portion 22R1,23R1 is the thickness 22T2 of the second portion 22R2,23R2. It is a point that is larger than 23T2. The first portion 22R1 of the lower electrode layer 22 of the trench capacitor 200 has a multilayer structure, and includes the first layer 22A and the second layer 22B. Similarly, the first portion 23R1 of the upper electrode layer 23 also has a multilayer structure, and includes the first layer 23A and the second layer 23B. The thickness 22T1,23T1 of the first portion 22R1,23R1 of the lower electrode layer 22 and the upper electrode layer 23 is set within a range of 2 times or more and 50 times or less of the thickness 22T2, 23T2 of the second portion 22R2, 23R2. .. In the embodiment shown in FIG. 5, the thickness 22T1 of the first portion 22R1 of the lower electrode layer 22 and the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 are substantially the same, but the thickness of the lower electrode layer 22 is the same. The thickness 22T1 of the one portion 22R1 and the thickness 23T1 of the first portion 23R1 of the upper electrode layer 23 may be different from each other. Further, the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22 and the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23 are substantially the same, but the thickness 22T2 of the second portion 22R2 of the lower electrode layer 22. And the thickness 23T2 of the second portion 23R2 of the upper electrode layer 23 may be different from each other.
 上記のトレンチキャパシタ200においては、下部電極層22及び上部電極層23の両方において、第1部分22R1,23R1の厚さ22T1,23T1が第2部分22R2,23R2の厚さ22T2,23T2よりも厚くなっている。したがって、トレンチキャパシタ1と同様の理由により、単位面積当たりの発生容量を保ちつつ、等価直列抵抗の更なる低下を図ることができる。 In the above trench capacitor 200, in both the lower electrode layer 22 and the upper electrode layer 23, the thickness 22T1,23T1 of the first portion 22R1,23R1 is thicker than the thickness 22T2,23T2 of the second portion 22R2,23R2. ing. Therefore, for the same reason as that of the trench capacitor 1, it is possible to further reduce the equivalent series resistance while maintaining the generated capacity per unit area.
 本明細書で説明された各構成要素の寸法、材料、及び配置は、実施形態中で明示的に説明されたものに限定されず、この各構成要素は、本発明の範囲に含まれうる任意の寸法、材料、及び配置を有するように変形することができる。また、本明細書において明示的に説明していない構成要素を、説明した実施形態に付加することもできるし、各実施形態において説明した構成要素の一部を省略することもできる。 The dimensions, materials, and arrangement of each component described herein are not limited to those expressly described in the embodiments, and each component may be included within the scope of the present invention. Can be transformed to have the dimensions, materials, and arrangement of. In addition, components not explicitly described in the present specification may be added to the described embodiments, or some of the components described in each embodiment may be omitted.
 本明細書において、一の物体が他の物体の「上」、「上面」、「下」、又は「下面」に設けられると説明される場合には、当該一の物体は当該他の物体と直接接していても良く、別の層や膜を介して間接的に接していても良い。 In the present specification, when it is described that one object is provided "above", "upper surface", "lower", or "lower surface" of another object, the one object is referred to as the other object. It may be in direct contact, or may be indirect contact via another layer or membrane.
 1…トレンチキャパシタ、10…基材、10a…上面、11…トレンチ、12…壁部、20…MIM構造体、21…誘電体層、22…下部電極層(第2導電層)、23…上部電極層(第1導電層)、22A,23A…第1層、22B,23B…第2層、22R1,23R1…第1部分、22R2,23R2…第2部分。 1 ... Trench capacitor, 10 ... Base material, 10a ... Top surface, 11 ... Trench, 12 ... Wall, 20 ... MIM structure, 21 ... Dielectric layer, 22 ... Lower electrode layer (second conductive layer), 23 ... Upper Electrode layer (first conductive layer), 22A, 23A ... 1st layer, 22B, 23B ... 2nd layer, 22R1, 23R1 ... 1st part, 22R2, 23R2 ... 2nd part.

Claims (12)

  1.  上面、前記上面とは反対側の下面、及び上下方向に沿って前記上面から延びるトレンチを有する基材と、
     複数の導電層及び前記複数の導電層に挟まれた誘電体層を有するMIM構造体と、を備え、
     前記複数の導電層のそれぞれは、前記トレンチ外に位置すると共に前記上面に沿って延びる第1部分と、前記トレンチ内に位置すると共に前記トレンチの前記壁面に沿って延びる第2部分と、を有し、
     前記複数の導電層のうち、少なくとも一の導電層の前記第1部分の厚さは、当該一の導電層の前記第2部分の厚さより大きい、トレンチキャパシタ。
    A substrate having an upper surface, a lower surface opposite to the upper surface, and a trench extending from the upper surface in the vertical direction.
    A MIM structure having a plurality of conductive layers and a dielectric layer sandwiched between the plurality of conductive layers.
    Each of the plurality of conductive layers has a first portion located outside the trench and extending along the upper surface, and a second portion located inside the trench and extending along the wall surface of the trench. And
    A trench capacitor in which the thickness of the first portion of at least one conductive layer among the plurality of conductive layers is larger than the thickness of the second portion of the one conductive layer.
  2.  前記複数の導電層は、前記誘電体層の上に位置する第1導電層を含み、
     前記第1導電層の前記第1部分の厚さは、前記第1導電層の前記第2部分の厚さより大きい、請求項1に記載のトレンチキャパシタ。
    The plurality of conductive layers include a first conductive layer located on the dielectric layer.
    The trench capacitor according to claim 1, wherein the thickness of the first portion of the first conductive layer is larger than the thickness of the second portion of the first conductive layer.
  3.  前記第1導電層の前記第1部分の厚さは、前記第1導電層の前記第2部分の厚さの2倍以上且つ50倍以下である、請求項2に記載のトレンチキャパシタ。 The trench capacitor according to claim 2, wherein the thickness of the first portion of the first conductive layer is twice or more and 50 times or less the thickness of the second portion of the first conductive layer.
  4.  前記第1導電層の前記第1部分は、第1層と、前記第1層の上に設けられた第2層と、
    を含む多層構造を有する、請求項2又は3に記載のトレンチキャパシタ。
    The first portion of the first conductive layer includes a first layer, a second layer provided on the first layer, and the like.
    The trench capacitor according to claim 2 or 3, which has a multilayer structure including.
  5.  前記複数の導電層は、前記誘電体層の下に位置する第2導電層を含み、
     前記第2導電層の前記第1部分の厚さは、前記第2導電層の前記第2部分の厚さより大きい、請求項1~4の何れか一項に記載のトレンチキャパシタ。
    The plurality of conductive layers include a second conductive layer located below the dielectric layer.
    The trench capacitor according to any one of claims 1 to 4, wherein the thickness of the first portion of the second conductive layer is larger than the thickness of the second portion of the second conductive layer.
  6.  前記第2導電層の前記第1部分の厚さは、前記第2導電層の前記第2部分の厚さの2倍以上且つ50倍以下である、請求項5に記載のトレンチキャパシタ。 The trench capacitor according to claim 5, wherein the thickness of the first portion of the second conductive layer is twice or more and 50 times or less the thickness of the second portion of the second conductive layer.
  7.  前記第2導電層の前記第1部分は、第1層と、前記第1層の上に設けられた第2層と、を含む多層構造を有する、請求項5又は6に記載のトレンチキャパシタ。 The trench capacitor according to claim 5 or 6, wherein the first portion of the second conductive layer has a multilayer structure including a first layer and a second layer provided on the first layer.
  8.  前記第2層を構成する材料の導電率は、前記第1層を構成する材料の導電率より高い、請求項4又は7に記載のトレンチキャパシタ。 The trench capacitor according to claim 4 or 7, wherein the conductivity of the material constituting the second layer is higher than the conductivity of the material constituting the first layer.
  9.  前記第1導電層の前記第1部分の厚さは、前記第2導電層の前記第1部分の厚さより大きい、請求項5~8の何れか一項に記載のトレンチキャパシタ。 The trench capacitor according to any one of claims 5 to 8, wherein the thickness of the first portion of the first conductive layer is larger than the thickness of the first portion of the second conductive layer.
  10.  請求項1~9の何れか一項に記載のトレンチキャパシタを備える、回路基板。 A circuit board including the trench capacitor according to any one of claims 1 to 9.
  11.  請求項10に記載の回路基板を備える、電子機器。 An electronic device including the circuit board according to claim 10.
  12.  上面、前記上面とは反対側の下面、及び上下方向に沿って前記上面から延びるトレンチを有する基材を準備する工程と、
     前記上面及び前記トレンチを画定する壁面に沿ってMIM構造体の導電層を形成する工程と、を備え、
     前記導電層を形成する工程は、化学気相成長を行う工程と、物理気相成長を行う工程とを含む、トレンチキャパシタの製造方法。
    A step of preparing a base material having an upper surface, a lower surface opposite to the upper surface, and a trench extending from the upper surface in the vertical direction.
    A step of forming a conductive layer of the MIM structure along the upper surface and the wall surface defining the trench is provided.
    The step of forming the conductive layer is a method for manufacturing a trench capacitor, which includes a step of performing chemical vapor deposition and a step of performing physical vapor deposition.
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JP2003297942A (en) * 2002-03-26 2003-10-17 Samsung Electronics Co Ltd Semiconductor device having metal-insulator-metal type capacitor and method for manufacturing the same
JP2006500772A (en) * 2002-09-23 2006-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション Structure and manufacturing method of MIM capacitor in dual damascene structure
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JP2003297942A (en) * 2002-03-26 2003-10-17 Samsung Electronics Co Ltd Semiconductor device having metal-insulator-metal type capacitor and method for manufacturing the same
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