JP2011066330A - Mounting substrate, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a mounting substrate in which an electrostatic capacitive element is built compact by limiting the size of the mounting substrate. <P>SOLUTION: An uneven shape A is formed on a top surface of a resin substrate, and a conductor is directly deposited so as to cover a top surface of the uneven shape of the resin substrate to form a lower electrode 20. A dielectric is directly deposited so as to cover a top surface of the lower electrode to form a dielectric film 21, and a conductor is directly deposited so as to cover a top surface of the dielectric film to form an upper electrode 22. A resin layer is formed on the upper electrode, and wiring is formed on the resin layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a mounting substrate and a method for manufacturing the same, and more particularly to a mounting substrate having a capacitive element and a method for manufacturing the same.

Capacitance elements formed in a semiconductor integrated circuit device are required to be miniaturized and highly integrated in portable devices and the like simultaneously with high frequency and high speed. In addition, a single component that functions as a capacitance element (capacitor) is used together with a mounting substrate (printed wiring board) or the like separately from the semiconductor integrated circuit device. Since the capacitance value of such a single component capacitance element is much larger than the capacitance value of the capacitance element formed in the semiconductor integrated circuit device, the single component capacitance element is placed in the semiconductor integrated circuit device. It is practically impossible to replace the capacitor element.
Therefore, in recent years, development of a technique for taking a capacitive element into a mounting substrate has been advanced.

  For example, in the past, a single component capacitive element has been mounted on the surface of a mounting board. However, as described in Patent Document 1, a method of embedding a single component capacitive element in a mounting board is proposed. Has been.

  However, the embedding of such a single component capacitance element has a problem of limiting the thickness of the mounting substrate. Therefore, a technology for forming a next generation capacitor element directly on a mounting substrate has been attracting attention.

A conventional capacitive element structure of a mounting substrate having a capacitive element has a structure in which, for example, as described in Patent Document 2, two flat plate-like electrodes arranged in parallel and a dielectric film are disposed therebetween. Are known.
Conventionally, a dielectric sheet or the like has been used as the dielectric film, but the thickness of the sheet is several μm, and it has been difficult to ensure a large capacity.
On the other hand, in recent years, attention has been focused on applying a thin film forming technique such as sputtering as a method of forming a dielectric film.

The capacitance value of the capacitive element can be generally expressed as the following formula (1). C is a capacitance value, ε ₀ is a dielectric constant in vacuum, ε is a relative dielectric constant of a dielectric film to be used, S is an electrode area, and T is a film thickness of the dielectric film.

[Equation 1]
C = ε ₀ · ε · S / T (1)

  As is apparent from this equation, in the conventional capacitive element having the parallel plate type electrode formed on the mounting substrate, the capacitance value is proportional to the electrode area. Therefore, in order to form a large capacity element, a large occupied area is required.

JP 2003-152303 A JP 2008-78547 A JP 2008-34694 A

  The problem to be solved is that it is difficult to reduce the size of the mounting substrate by limiting the size of the mounting substrate in the conventional capacitive element structure built in the mounting substrate.

  The method for manufacturing a mounting substrate according to the present invention includes a step of forming an uneven shape on the surface of a resin substrate, and a step of forming a lower electrode by directly depositing a conductor so as to cover the surface of the uneven shape of the resin substrate. Forming a dielectric film by directly depositing a dielectric so as to cover the surface of the lower electrode; and forming an upper electrode by directly depositing a conductor so as to cover the surface of the dielectric film A step of forming a resin layer on the upper layer of the upper electrode, and a step of forming a wiring on the upper layer of the resin layer.

  In the method for manufacturing a mounting substrate according to the present invention, an uneven shape is formed on the surface of the resin substrate, and a conductor is directly deposited so as to cover the uneven surface of the resin substrate to form a lower electrode. Next, a dielectric is directly deposited so as to cover the surface of the lower electrode to form a dielectric film. Next, a conductor is directly deposited so as to cover the surface of the dielectric film to form an upper electrode. Next, a resin layer is formed on the upper layer of the upper electrode, and wiring is formed on the upper layer of the resin layer.

  The mounting substrate of the present invention includes a resin substrate having a concavo-convex shape formed on a surface thereof, a lower electrode formed by directly depositing a conductor so as to cover the concavo-convex surface of the resin substrate, and the lower electrode A dielectric film formed by directly depositing a dielectric so as to cover the surface of the dielectric, an upper electrode formed by directly depositing a conductor so as to cover the surface of the dielectric film, and the upper electrode A resin layer formed on the upper layer, and a wiring formed on the upper layer of the resin layer.

  In the mounting board of the present invention described above, the lower electrode is formed by directly depositing a conductor so as to cover the uneven surface of the resin substrate having the uneven surface formed thereon, and covers the surface of the lower electrode. Thus, a dielectric is directly deposited to form a dielectric film, and a conductor is directly deposited to cover the surface of the dielectric film to form an upper electrode. Further, a resin layer is formed on the upper layer of the upper electrode, and wiring is formed on the upper layer of the resin layer.

  According to the method for manufacturing a mounting board of the present invention, a capacitive element can be formed in the mounting board (printed wiring board). As a result, by replacing with a single component capacitive element, the number of single component capacitive elements used can be reduced, and the mounting cost and the like can be reduced. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

  According to the mounting board of the present invention, the mounting board (printed wiring board) has a capacitive element, and the number of single-piece capacitive elements used can be reduced by replacing the single-piece capacitive element. This makes it possible to reduce mounting costs. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

FIG. 1A is a schematic cross-sectional view of a mounting substrate according to the first embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view in which a portion of a capacitance element is enlarged. 2A and 2B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 3A and 3B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 4A and 4B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. 5A and 5B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the first embodiment of the present invention. FIG. 6 is an enlarged schematic cross-sectional view of a portion of the capacitive element of the mounting substrate according to the second embodiment of the present invention. 7A and 7B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention. 8A and 8B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention. FIGS. 9A and 9B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention. FIGS. 10A and 10B are schematic cross-sectional views showing a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention. 11A and 11B are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the second embodiment of the present invention.

  Embodiments of a mounting substrate and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

The description will be given in the following order.
1. First Embodiment (Mounting substrate in which a capacitive element is formed on an uneven portion formed by etching)
2. Second Embodiment (Mounting Substrate with Capacitance Element Formed on Concave and Shaped Part Formed by Stamper Press)

<First Embodiment>
[Configuration of entire mounting board]
FIG. 1A is a schematic cross-sectional view of a mounting substrate according to the present embodiment.
The resin substrate 1 is configured by, for example, laminating a plurality of resin layers, the internal wiring 2 and the inter-wiring contact 3 are embedded therein, the surface wiring 4 is formed on the surface, and the mounting substrate is It is configured.
For example, as shown in FIG. 1A, the mounting substrate of the present embodiment is used by mounting the semiconductor chip 5 on a flip chip via bumps. Alternatively, other electronic elements can be mounted. It can also be mounted by a method other than flip chip.
Here, the capacitive element 6 is formed on the mounting substrate according to the present embodiment. The place where the electrostatic capacitance element 6 is formed is not limited to the uppermost layer of the mounting substrate.

[Configuration of capacitance element]
FIG. 1B is an enlarged schematic cross-sectional view of a portion of the capacitive element 6 formed on the mounting substrate according to the present embodiment.
For example, the first conductive layer 11 is formed on the upper layer of the first resin layer 10, the second resin layer 12 is laminated on the upper layer, and the second conductive layer 13 is formed on the upper layer.
Here, the first resin layer 10 and the second resin layer 12 are resin layers constituting the resin substrate, and the first conductive layer 11 and the second conductive layer 13 are conductive layers constituting the internal wiring of the resin substrate.

For example, a plurality of openings reaching the first conductive layer 11 are opened with respect to the second conductive layer 13 and the second resin layer 12, and an uneven shape A is formed.
The lower electrode 20 is formed so as to cover the surface of the uneven shape A. The lower electrode 20 is a film formed by directly depositing a conductor so as to cover the surface of the concavo-convex shape A.
A dielectric film 21 is formed so as to cover the surface of the lower electrode 20. The dielectric film 21 is a film formed by directly depositing a dielectric so as to cover the surface of the lower electrode 20.
An upper electrode 22 is formed so as to cover the surface of the dielectric film 21. The upper electrode 22 is a film formed by directly depositing a conductor so as to cover the surface of the dielectric film 21.
With the above-described configuration, a capacitive element in which the lower electrode 20, the dielectric film 21, and the upper electrode 22 are stacked is configured.
The lower electrode 20 is formed to be connected to the first conductive layer 11 and the second conductive layer 13, and the lower electrode is constituted by the lower electrode 20, the first conductive layer 11 and the second conductive layer 13. it can. Thereby, the parasitic resistance of the lower electrode 20 can be reduced, and a capacitance element suitable for high-frequency circuit applications can be obtained.

  The dielectric film 21 is a film formed by, for example, an atomic layer deposition (ALD) method. The dielectric film 21 is made of, for example, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, or a stacked or mixed material of these materials. Alternatively, a material obtained by adding another element to the above material is used.

  The lower electrode 20 and the upper electrode 22 are, for example, films formed by an atomic layer deposition method, respectively. The lower electrode 20 and the upper electrode 22 are made of, for example, a metal material such as Ru, Mo, or Pt, or a nitride of a metal element contained in the dielectric material of the dielectric film 21, such as hafnium nitride, zirconium nitride, or tantalum nitride. Conductive nitrides such as titanium nitride are used. In the case of conductive nitride, it is possible to prevent oxygen in the dielectric film from diffusing into the first conductive layer 11 or the second conductive layer 13.

Further, for example, the third conductive layer 24 is formed on the upper layer of the upper electrode 22, the third resin layer 30 is laminated on the upper layer, and the fourth conductive layer 31 is formed on the upper layer. The third conductive layer 24 is formed to be connected to the upper electrode 22, and it can be said that the upper electrode is constituted by the upper electrode 22 and the third conductive layer 24.
Here, the third resin layer 30 is a resin layer constituting the resin substrate, and the fourth conductive layer 31 is a conductive layer constituting the wiring on the surface of the resin substrate.

Further, for example, an opening CT1 reaching the third conductive layer 24 is formed in the fourth conductive layer 31 and the third resin layer 30, and the extraction electrode 32 connected to the third conductive layer 24 constituting the upper electrode. Is formed.
Further, for example, an opening CT2 reaching the first conductive layer 11 is formed in the fourth conductive layer 31, the third resin layer 30, and the second resin layer 12, and the first conductive layer 11 constituting the lower electrode is formed. A take-out electrode 33 connected to is formed.
As described above, the capacitive element of the mounting board according to the present embodiment is configured.

  The capacitance element formed on the mounting substrate of the present embodiment has a configuration in which the lower electrode, the dielectric film, and the upper electrode are laminated so as to cover the uneven surface formed on the resin substrate. The effective electrode area can be increased with respect to the area occupied by the element. Thereby, it is possible to obtain a large-capacity element with a small occupied area.

[Method of forming electrostatic capacitance element]
2 to 5 are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the present embodiment.
First, as shown in FIG. 2A, for example, the first conductive layer 11 is formed on the upper layer of the first resin layer 10, the second resin layer 12 is laminated on the upper layer, and the second conductive layer is formed on the upper layer. 13 is formed. These can be formed, for example, by bonding the first resin layer 10 on which the first conductive layer 11 is formed and the second resin layer 12 on which the second conductive layer 13 is formed.
Here, the first resin layer 10 and the second resin layer 12 are resin layers constituting the resin substrate, and the first conductive layer 11 and the second conductive layer 13 constitute internal wiring of the resin substrate in other regions. To form.

  Next, as shown in FIG. 2B, for example, a dry film 14 or the like having an opening in a desired region is patterned, the second conductive layer 13 is patterned and opened, and then laser processing or the like is performed, for example. Then, the second resin layer 12 is opened. As described above, the concavo-convex shape A formed by opening a plurality of openings reaching the first conductive layer 11 is formed in the second conductive layer 13 and the second resin layer. The opening diameter of the opening is, for example, about 10 nm to 1 μm, and specifically 100 nm.

Next, as shown in FIG. 3A, for example, the lower electrode 20, the dielectric film 21, and the upper electrode 22 are continuously formed.
Here, a conductor is directly deposited to cover the surface of the concavo-convex shape A to form the lower electrode 20, and a dielectric is directly deposited to cover the surface of the lower electrode 20 to form the dielectric film 21. Then, a conductor is directly deposited so as to cover the surface of the dielectric film 21 to form the upper electrode 22.

As a method of forming the dielectric film 21, for example, it is preferable to form the dielectric film 21 by low-temperature film formation in which the resin substrate is formed at a temperature lower than the temperature at which the resin substrate is damaged. Here, the heat resistant temperature of the resin substrate is, for example, 150 ° C., and the temperature for low-temperature film formation is about 100 to 130 ° C.
As a method for realizing low-temperature film formation, for example, a plasma ALD method in which oxidation or nitridation is performed by a plasma reaction using oxygen or ozone as an oxidation source, nitrogen or ammonia as a nitridation source, and the like can be used. In the case of an oxide film, a thermal ALD method using hydrolysis in which a reaction between an organic material containing silicon or metal and H ₂ O proceeds even at a low temperature can be used.
Alternatively, the dielectric film is formed by using a low temperature plasma CVD (Chemical Vapor Deposition) method using a high density plasma source such as ECR (Electron Cyclotron Resonance) or a low temperature thermal CVD method using hydrolysis. May be performed.

  For example, it is preferable to use an ALD method with good step coverage. Examples of the dielectric material constituting the dielectric film 21 include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, and these materials. A material obtained by stacking or mixing these materials, or a material obtained by adding another element to the above materials can be used.

The lower electrode 20 and the upper electrode 22 are preferably formed using an ALD method with good step coverage.
As the conductive material, a conductive material such as a metal material such as Ru, Mo, Pt, or a nitride of a metal element contained in the dielectric material of the dielectric film 21, such as hafnium nitride, zirconium nitride, tantalum nitride, or titanium nitride. A reactive nitride material is used. This is effective in preventing oxygen in the dielectric film from diffusing into the first conductive layer 11 or the second conductive layer 13.
By the above ALD method, the lower electrode 20, the dielectric film 21, and the upper electrode 22 can be continuously formed.

  The lower electrode 20 is formed to be connected to the first conductive layer 11 and the second conductive layer 13, and the lower electrode is constituted by the lower electrode 20, the first conductive layer 11 and the second conductive layer 13. it can. Thereby, the parasitic resistance of the lower electrode 20 can be reduced, and a capacitance element suitable for high-frequency circuit applications can be formed.

  Next, as shown in FIG. 3B, for example, a resist 23 is patterned so as to open a desired region in the upper layer of the upper electrode 22. For example, the third conductive layer 24 is formed by an electroless plating method using a palladium catalyst or the like using the resist 23 as a mask.

  Next, the resist 23 is removed, and as shown in FIG. 4A, for example, the dry film 25 is patterned so as to open the desired region while protecting the region of the capacitive element. Etching is performed using the dry film 25 as a mask, and the upper electrode 22, the dielectric film 21, and the lower electrode 20 are patterned.

  Next, the dry film 25 is removed, and as shown in FIG. 4B, for example, the dry film 26 is patterned so as to protect the area of the capacitive element and open a desired area. Here, it is formed so as to protect an area wider than the dry film 25. Etching is performed using the dry film 26 as a mask to pattern the second conductive layer 13.

Next, as shown in FIG. 5A, for example, the third resin layer 30 is formed on the entire surface of the third conductive layer 24, and the fourth conductive layer 31 is formed thereon. For example, the third resin layer 30 on which the fourth conductive layer 31 is formed can be formed by bonding by pressing or the like.
Next, for example, the opening CT1 reaching the third conductive layer 24 is formed in the fourth conductive layer 31 and the third resin layer 30. For example, a dry film having a contact region with respect to the upper electrode is patterned, the fourth conductive layer 31 is opened by pattern etching, and then the third resin layer 30 is opened by, for example, laser processing. .
Similarly to the above, an opening CT2 reaching the first conductive layer 11 is formed in the fourth conductive layer 31, the third resin layer 30, and the second resin layer 12. For example, a dry film having a contact region with respect to the lower electrode is patterned, the fourth conductive layer 31 is patterned and opened, and then the third resin layer 30 and the second resin layer 12 are formed by, for example, laser processing. The opening is formed.

Next, as shown in FIG. 5B, for example, a conductive layer is formed by filling the opening CT1, and the extraction electrode 32 connected to the third conductive layer 24 constituting the upper electrode is formed.
At the same time as described above, for example, the conductive layer is formed by filling the opening CT2, and the extraction electrode 33 connected to the first conductive layer 11 constituting the lower electrode is formed.

  According to the method for manufacturing a mounting board of the present invention, a capacitive element can be formed in the mounting board (printed wiring board). As a result, by replacing with a single component capacitive element, the number of single component capacitive elements used can be reduced, and the mounting cost and the like can be reduced. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

  In the mounting substrate manufacturing method of the present embodiment, there is no limitation on the number of resin layers that are concave and convex for forming the capacitive element. Deeper irregularities A can be formed by laser processing two or more resin layers, and a larger capacitance value can be obtained.

Second Embodiment
[Configuration of capacitance element]
The mounting board according to the present embodiment has substantially the same configuration as that of the mounting board according to the first embodiment, and the capacitance element portion is different as follows.
FIG. 6 is an enlarged schematic cross-sectional view of a portion of the capacitive element formed on the mounting substrate according to the present embodiment.
For example, the first conductive layer 41 is formed on the upper layer of the first resin layer 40, the second resin layer 42 is laminated on the upper layer, and the second conductive layer 43 is formed on the upper layer.
Here, the first resin layer 40 and the second resin layer 42 are resin layers constituting the resin substrate, and the first conductive layer 41 and the second conductive layer 43 are conductive layers constituting the internal wiring of the resin substrate.

For example, the second conductive layer 43 is removed in the formation region of the capacitive element. In the formation region of the electrostatic capacitance element, a plurality of openings are opened to the second resin layer 42 and the first resin layer 40, and an uneven shape A is formed.
A lower electrode 50 is formed so as to cover the surface of the concavo-convex shape A. The lower electrode 50 is a film formed by directly depositing a conductor so as to cover the surface of the concavo-convex shape A.
A dielectric film 51 is formed so as to cover the surface of the lower electrode 50. The dielectric film 51 is a film formed by directly depositing a dielectric so as to cover the surface of the lower electrode 50.
An upper electrode 52 is formed so as to cover the surface of the dielectric film 51. The upper electrode 52 is a film formed by directly depositing a conductor so as to cover the surface of the dielectric film 51.
With the above-described configuration, a capacitive element in which the lower electrode 50, the dielectric film 51, and the upper electrode 52 are stacked is configured.
The lower electrode 50 is formed to be connected to the second conductive layer 43, and it can be said that the lower electrode is constituted by the lower electrode 50 and the second conductive layer 43.

  The dielectric film 51 is a film formed by, for example, an atomic layer deposition (ALD) method. The dielectric film 51 includes, for example, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, and a stacked or mixed material of these materials, Alternatively, a material obtained by adding another element to the above material is used.

  The lower electrode 50 and the upper electrode 52 are, for example, films formed by an atomic layer deposition method, respectively. The lower electrode 50 and the upper electrode 52 are made of, for example, a metal material such as Ru, Mo, or Pt, or a nitride of a metal element contained in the dielectric material of the dielectric film 21, such as hafnium nitride, zirconium nitride, or tantalum nitride. Conductive nitrides such as titanium nitride are used. In the case of conductive nitride, oxygen in the dielectric film can be prevented from diffusing into the second conductive layer 43 and the like.

Further, for example, the third conductive layer 54 is formed on the upper layer of the upper electrode 52, the third resin layer 60 is laminated on the upper layer, and the fourth conductive layer 61 is formed on the upper layer. The third conductive layer 54 is formed to be connected to the upper electrode 52, and it can be said that the upper electrode is constituted by the upper electrode 52 and the third conductive layer 54.
Here, the third resin layer 60 is a resin layer constituting the resin substrate, and the fourth conductive layer 61 is a conductive layer constituting the wiring on the surface of the resin substrate.

For example, an opening CT1 reaching the third conductive layer 54 is formed in the fourth conductive layer 61 and the third resin layer 60, and the extraction electrode 62 connected to the third conductive layer 54 constituting the upper electrode. Is formed.
Further, for example, an opening CT2 reaching the second conductive layer 43 is formed in the fourth conductive layer 61 and the third resin layer 60, and the extraction electrode 63 connected to the second conductive layer 43 constituting the lower electrode. Is formed.
As described above, the capacitive element of the mounting board according to the present embodiment is configured.

  The capacitance element formed on the mounting substrate of the present embodiment has a configuration in which the lower electrode, the dielectric film, and the upper electrode are laminated so as to cover the uneven surface formed on the resin substrate. The effective electrode area can be increased with respect to the area occupied by the element. Thereby, it is possible to obtain a large-capacity element with a small occupied area.

[Method of forming electrostatic capacitance element]
7 to 11 are schematic cross-sectional views illustrating a method for forming a capacitive element of a mounting board according to the present embodiment.
First, as shown in FIG. 7A, for example, a first conductive layer 41 is formed on an upper layer of the first resin layer 40, a second resin layer 42 is stacked thereon, and a second conductive layer is formed on the upper layer. 43 is formed. These can be formed, for example, by bonding the first resin layer 40 on which the first conductive layer 41 is formed and the second resin layer 42 on which the second conductive layer 43 is formed.
Here, the first resin layer 40 and the second resin layer 42 are resin layers constituting the resin substrate, and the first conductive layer 41 and the second conductive layer 43 constitute internal wiring of the resin substrate in other regions. To form.

  Next, as shown in FIG. 7B, for example, a dry film 44 or the like having an opening in the formation region of the capacitive element is patterned, and the second conductive layer 43 is opened by pattern etching.

Next, as shown in FIG. 8A, for example, the stamper 45 is pressed against the second resin layer 42 in the formation region of the capacitive element, and the stamper is released as shown in FIG. 8B. Thereby, the 2nd resin layer 42 and the 1st resin layer 40 are opened to predetermined depth, and uneven | corrugated shape A is formed. This is a method using a so-called nanoprint technology, and the second resin layer 42 and the first resin layer 40 can be implemented by using a prepreg (B stage) before complete curing.
At this time, in order to prevent the concavo-convex shape A from collapsing, it is preferable that a release material is provided on the surface of the stamper 45. As a result, it is possible to form the concavo-convex shape A with good reproducibility, and to realize a reduction in variation in capacitance value.
The opening diameter of the opening is, for example, about 10 nm to 1 μm, and specifically 100 nm.

Next, as shown in FIG. 9A, for example, the lower electrode 50, the dielectric film 51, and the upper electrode 52 are continuously formed.
Here, a conductor is directly deposited to cover the surface of the concavo-convex shape A to form the lower electrode 50, and a dielectric is directly deposited to cover the surface of the lower electrode 50 to form the dielectric film 51. Then, an upper electrode 52 is formed by directly depositing a conductor so as to cover the surface of the dielectric film 51.

As a method for forming the dielectric film 51, for example, it is preferable to form the dielectric film 51 by low-temperature film formation in which the resin substrate is formed at a temperature lower than the temperature at which the resin substrate is damaged. Here, the heat resistant temperature of the resin substrate is, for example, 150 ° C., and the temperature for low-temperature film formation is about 100 to 130 ° C.
As a method for realizing low-temperature film formation, for example, a plasma ALD method in which oxidation or nitridation is performed by a plasma reaction using oxygen or ozone as an oxidation source, nitrogen or ammonia as a nitridation source, and the like can be used. In the case of an oxide film, a thermal ALD method using hydrolysis in which a reaction between an organic material containing silicon or metal and H ₂ O proceeds even at a low temperature can be used.
Alternatively, the dielectric film may be formed using a low-temperature plasma CVD method using a high-density plasma source such as ECR, or a low-temperature thermal CVD method using hydrolysis.

  For example, it is preferable to use an ALD method with good step coverage. Examples of the dielectric material constituting the dielectric film 51 include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, barium titanate, barium strontium titanate, and these materials. A material obtained by stacking or mixing these materials, or a material obtained by adding another element to the above materials can be used.

The lower electrode 50 and the upper electrode 52 are preferably formed using the ALD method with good step coverage.
As the conductive material, a conductive material such as a metal material such as Ru, Mo, or Pt, or a nitride of a metal element contained in the dielectric material of the dielectric film 51, such as hafnium nitride, zirconium nitride, tantalum nitride, or titanium nitride, is used. A reactive nitride material is used. This is effective in preventing oxygen in the dielectric film from diffusing into the second conductive layer 43 and the like.
By the ALD method, the lower electrode 50, the dielectric film 51, and the upper electrode 52 can be continuously formed.

  The lower electrode 50 is formed to be connected to the second conductive layer 43, and it can be said that the lower electrode is composed of the lower electrode 50 and the second conductive layer 43.

  Next, as shown in FIG. 9B, for example, a resist 53 is patterned so as to open a desired region in the upper layer of the upper electrode 52. For example, the third conductive layer 54 is formed by an electroless plating method using a palladium catalyst or the like using the resist 53 as a mask.

  Next, the resist 53 is removed, and, as shown in FIG. 10A, for example, the dry film 55 is patterned so as to open the desired region while protecting the region of the capacitive element. Etching is performed using the dry film 55 as a mask, and the upper electrode 52, the dielectric film 51, and the lower electrode 50 are patterned.

  Next, the dry film 55 is removed, and as shown in FIG. 10B, for example, the dry film 56 is patterned so as to protect the area of the capacitive element and open a desired area. Here, a region wider than the dry film 55 is protected. Etching is performed using the dry film 56 as a mask to pattern the second conductive layer 43.

Next, as shown in FIG. 11A, for example, the third resin layer 60 is formed on the entire surface of the third conductive layer 54, and the fourth conductive layer 61 is formed thereon. For example, the third resin layer 60 on which the fourth conductive layer 61 is formed can be formed by bonding by pressing.
Next, for example, the opening CT <b> 1 reaching the third conductive layer 54 is formed in the fourth conductive layer 61 and the third resin layer 60. For example, a dry film having a contact region with respect to the upper electrode is patterned, the fourth conductive layer 61 is opened by pattern etching, and then the third resin layer 60 is opened by, for example, laser processing. .
Similarly to the above, an opening CT2 reaching the second conductive layer 43 is formed in the fourth conductive layer 61 and the third resin layer 60. For example, a dry film having a contact region with respect to the lower electrode is patterned, the fourth conductive layer 61 is opened by pattern etching, and then the third resin layer 60 is opened by, for example, laser processing. .

Next, as shown in FIG. 11B, for example, a conductive layer is formed by filling the inside of the opening CT1, and the extraction electrode 62 connected to the third conductive layer 54 constituting the upper electrode is formed.
At the same time as described above, for example, a conductive layer is formed by filling the inside of the opening CT2, and an extraction electrode 63 connected to the second conductive layer 43 constituting the lower electrode is formed.

  According to the method for manufacturing a mounting board of the present invention, a capacitive element can be formed in the mounting board (printed wiring board). As a result, by replacing with a single component capacitive element, the number of single component capacitive elements used can be reduced, and the mounting cost and the like can be reduced. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

  In the mounting substrate manufacturing method of the present embodiment, there is no limitation on the number of resin layers that are concave and convex for forming the capacitive element. By processing the two or more resin layers with a nanoprint technique using a stamper, it is possible to form a deeper uneven shape A and obtain a larger capacitance value.

  According to the method for manufacturing the mounting board according to the present embodiment, the capacitive element can be formed in the mounting board (printed wiring board). As a result, by replacing with a single component capacitive element, the number of single component capacitive elements used can be reduced, and the mounting cost and the like can be reduced. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

  According to the mounting board of this embodiment, the mounting board (printed wiring board) has a capacitive element. By replacing the capacitive element with a single component, the number of single-component capacitive elements used can be reduced. It is possible to reduce the mounting cost and the like. Further, if a large-capacity capacitive element can be formed, the occupied area is reduced, so that the mounting substrate can be reduced in size.

The present invention is not limited to the above description.
For example, the depth of the opening having an uneven shape can be appropriately selected according to the thickness of the resin layer, the depth of the conductive layer, and the like. The number of openings can be appropriately selected according to the required capacitance value of the capacitance element and the occupied area that can be secured.
In addition, various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Resin board | substrate, 2 ... Internal wiring, 3 ... Contact between wiring, 4 ... Surface wiring, 5 ... Semiconductor chip, 6 ... Electrostatic capacitance element 10, 40 ... 1st resin layer, 11, 41 ... 1st conductive layer , 12, 42 ... second resin layer, 13, 43 ... second conductive layer, 14, 44 ... dry film, 20, 50 ... lower electrode, 21, 51 ... dielectric film, 22, 52 ... upper electrode, 23. 53: Resist, 24, 54: Third conductive layer, 25, 26, 55, 56: Dry film, 30, 60: Third resin layer, 31, 61: Fourth conductive layer, 32, 33, 62, 63 ... Extraction electrode, 45 ... stamper, A ... uneven shape, CT1, CT2 ... opening

Claims (12)

Forming a concavo-convex shape on the surface of the resin substrate;
Forming a lower electrode by directly depositing a conductor so as to cover the uneven surface of the resin substrate;
Forming a dielectric film by directly depositing a dielectric so as to cover the surface of the lower electrode;
Forming a top electrode by directly depositing a conductor so as to cover the surface of the dielectric film;
Forming a resin layer on the upper electrode;
Forming a wiring on an upper layer of the resin layer. After the step of forming the resin layer,
Forming each of an opening reaching the lower electrode and an opening reaching the upper electrode;
The method of manufacturing a mounting substrate according to claim 1, further comprising: forming an extraction electrode connected to each of the lower electrode and the upper electrode in the opening reaching the lower electrode and the opening reaching the upper electrode. The method for manufacturing a mounting substrate according to claim 1, wherein the dielectric film is formed by atomic layer deposition in the step of forming the dielectric film. The method for manufacturing a mounting substrate according to claim 3, wherein the formation is performed by atomic layer deposition in the step of forming the lower electrode and the step of forming the upper electrode. A resin substrate having a conductive layer serving as an internal wiring is used as the resin substrate, and in the step of forming an uneven shape on the surface of the resin substrate, the resin substrate is pattern-etched using the conductive layer as an etching stopper to form an uneven shape. The manufacturing method of the mounting substrate of Claim 1. The manufacturing method of the mounting substrate according to claim 1, wherein in the step of forming the concavo-convex shape on the surface of the resin substrate, the concavo-convex shape is formed by pressing a stamper serving as a concavo-convex mold onto the resin substrate before complete curing. A resin substrate having a concavo-convex shape formed on the surface;
A lower electrode formed by directly depositing a conductor so as to cover the uneven surface of the resin substrate;
A dielectric film formed by directly depositing a dielectric so as to cover the surface of the lower electrode;
An upper electrode formed by directly depositing a conductor so as to cover the surface of the dielectric film;
A resin layer formed on the upper electrode;
And a wiring board formed on the resin layer. An opening reaching the lower electrode and an opening reaching the upper electrode are formed in the resin layer,
The mounting substrate according to claim 7, wherein an extraction electrode connected to each of the lower electrode and the upper electrode is formed in an opening reaching the lower electrode and an opening reaching the upper electrode. The mounting substrate according to claim 7, wherein the dielectric film is a film formed by atomic layer deposition. The mounting substrate according to claim 9, wherein each of the lower electrode and the upper electrode is a film formed by atomic layer deposition. The mounting substrate according to claim 7, wherein the resin substrate is a resin substrate having a conductive layer serving as an internal wiring, and the uneven shape is an uneven shape formed by an opening that reaches the conductive layer. The mounting substrate according to claim 7, wherein the concavo-convex shape is a shape formed by pressing a stamper serving as a concavo-convex shape mold on the resin substrate.

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