JP2018148086A - Manufacturing method for through electrode substrate and through electrode substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a through electrode substrate in which a wiring layer does not become thick, by making a seed layer thin when forming the seed layer on a substrate surface and a sidewall of a hole.SOLUTION: A manufacturing method for a through electrode substrate includes a step of preparing a substrate where a sidewall 21 of a through hole 20 of the substrate is tapered from a substrate first surface 13 across a second surface 14, and an angle α formed by the sidewall 21 of the through hole and a normal direction nd of the substrate is 1.0 degrees or more, a step of forming a seed layer 221 on the first surface 13, the second surface 14 of the substrate and the through hole 20, by using at least one of physical vapor deposition and sputtering, and a step of forming a plating layer 222 on the seed layer. In the step of forming the seed layer 221, the seed layers of the first and second wiring layers 31, 41 are formed so that the seed layers of the first and second wiring layers 31, 41 have respective thicknesses of 1.0 μm or more, and the seed layer 221 of the through electrode is formed on the sidewall 21 of the through hole.SELECTED DRAWING: Figure 2

Description

  Embodiments of the present disclosure relate to a method for manufacturing a through electrode substrate. The present invention also relates to a through electrode substrate.

  For example, as disclosed in Patent Document 1, the through electrode substrate includes a substrate including a first surface and a second surface, a plurality of holes provided in the substrate, and a first surface side to a second surface side of the substrate. And an electrode portion provided inside the hole. Such a through electrode substrate has been conventionally used for various purposes, and is mounted on an electronic device such as a mobile phone. In the following description, the electrode portion is referred to as a through electrode.

  Such a through electrode of the through electrode substrate may be formed by performing a plating process after forming a seed layer on the side wall of the hole of the substrate. In this case, vapor deposition or sputtering can be used to form the seed layer.

JP 2011-3925 A

  When the seed layer is formed by vapor deposition or sputtering, the seed layer may be simultaneously formed on the substrate surface and the side wall of the hole, and the seed layer on the substrate surface may be used as a part of the wiring layer. Thus, when forming a seed layer on the substrate surface and the sidewall of the hole, the seed layer is less likely to adhere to the sidewall of the hole compared to the substrate surface, so it is necessary to ensure a long processing time for vapor deposition or sputtering. is there. For these reasons, in many conventional through electrode substrates, the seed layer laminated on the substrate surface is thick, and the wiring layer on the substrate surface formed through plating is also thick. Therefore, there is room for improvement in efficient production and thinning of the seed layers of the wiring layer and the through electrode.

  When the wiring layer on the substrate surface is thick as described above, the amount of side etching when patterning the wiring layer by etching increases. Therefore, there is room for improvement in efficiently patterning the wiring layer.

  Embodiments of the present disclosure have been made in view of the above circumstances, and a through electrode substrate manufacturing method and a through electrode capable of efficiently manufacturing a through electrode substrate that contributes to thinning of a device to be mounted An object is to provide an electrode substrate.

  One embodiment of the present disclosure is a substrate including a first surface and a second surface located on the opposite side of the first surface and provided with a through hole, and a side wall of the through hole is formed from the first surface. Providing a substrate having a taper shape that tapers across the second surface, and an angle formed between a side wall of the through hole and a normal direction of the substrate is 1.0 degree or more; Forming a seed layer on the first surface, the second surface, and the through-hole using at least one of physical vapor deposition and sputtering, and forming a plating layer on the seed layer, A conductive first wiring layer positioned on the first surface, a conductive second wiring layer positioned on the second surface, and a through electrode positioned in the through hole are formed. And the step of forming the seed layer includes: Forming the seed layer of the first wiring layer and the seed layer of the second wiring layer so that the thickness of the seed layer of one wiring layer and the seed layer of the second wiring layer is 1.0 μm or more; It is a manufacturing method of the penetration electrode substrate which forms the seed layer of the penetration electrode in the side wall of the penetration hole.

  In addition, an embodiment of the present disclosure is a substrate including a first surface and a second surface located on the opposite side of the first surface and provided with a through hole, and a side wall of the through hole is the first surface. Providing a substrate having a taper shape that tapers from a surface to the second surface, and an angle formed between a side wall of the through hole and a normal direction of the substrate is 0.8 degrees or more; Forming a seed layer on the first surface, the second surface and the through-hole of the substrate by using at least one of physical vapor deposition and sputtering, and forming a plating layer on the seed layer; A conductive first wiring layer located on the first surface; a conductive second wiring layer located on the second surface; and a through electrode located in the through hole; A step of forming the seed layer. The seed layer of the first wiring layer and the seed layer of the second wiring layer are formed such that the thicknesses of the seed layer of the first wiring layer and the seed layer of the second wiring layer are 1.5 μm or more. And a through electrode substrate manufacturing method in which a seed layer of the through electrode is formed on a side wall of the through hole.

  In the method for manufacturing a through electrode substrate according to an embodiment of the present disclosure, the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer may each be formed by sputtering. .

  Further, in the method of manufacturing the through electrode substrate according to the embodiment of the present disclosure, in the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the second wiring layer have a thickness of 3.0 μm or less. You may form in the range.

  In the method for manufacturing a through electrode substrate according to an embodiment of the present disclosure, an angle formed between the side wall of the through hole and the normal direction of the substrate may be 12 degrees or less.

  In the method for manufacturing the through electrode substrate according to the embodiment of the present disclosure, the thickness of the substrate may be not less than 300 μm and not more than 400 μm.

  In addition, an embodiment of the present disclosure is a substrate including a first surface and a second surface located on the opposite side of the first surface, and provided with a through hole, wherein the side wall of the through hole has the first surface. A tapered first side wall portion that tapers from one surface toward the inner side of the substrate; and a tapered second side wall portion that tapers from the second surface toward the inner side of the substrate; A step of preparing a substrate in which an angle formed between each of the first sidewall portion and the second sidewall portion of the through hole and a normal direction of the substrate is 1.0 degree or more; Forming a seed layer on the first surface, the second surface and the through-hole using at least one of physical vapor deposition and sputtering, and forming a plating layer on the seed layer, A first wiring layer located on the first surface and having conductivity, and the second surface; Forming a conductive second wiring layer and a penetrating electrode located in the through hole, and in the step of forming the seed layer, the seed layer of the first wiring layer And forming the seed layer of the first wiring layer and the seed layer of the second wiring layer so that each thickness of the seed layer of the second wiring layer is 1.0 μm or more, and forming the seed layer on the sidewall of the through hole. It is a manufacturing method of the penetration electrode substrate which forms the seed layer of the penetration electrode.

  In the method for manufacturing a through electrode substrate according to an embodiment of the present disclosure, the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer may each be formed by sputtering. .

  Further, in the method of manufacturing the through electrode substrate according to the embodiment of the present disclosure, in the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the second wiring layer have a thickness of 3.0 μm or less. You may form in the range.

  In the method for manufacturing a through electrode substrate according to an embodiment of the present disclosure, an angle formed between the side wall of the through hole and the normal direction of the substrate may be 12 degrees or less.

  In the method for manufacturing the through electrode substrate according to the embodiment of the present disclosure, the thickness of the substrate may be not less than 300 μm and not more than 400 μm.

  In addition, an embodiment of the present disclosure includes a substrate including a first surface and a second surface positioned on the opposite side of the first surface and provided with a through hole, and is disposed on the first surface and is electrically conductive. A first wiring layer having conductive properties, a second wiring layer located on the second surface and having conductivity, and a through electrode positioned in the through hole, wherein a side wall of the through hole has the first surface The taper is tapered from the second surface to the second surface, and the angle formed between the side wall of the through hole and the normal direction of the substrate is 1.0 degree or more. Conformal vias provided on the sidewalls of the first and second wiring layers are electrically connected to each other, and the through electrode, the first wiring layer, and the second wiring layer are respectively A seed layer and a plating layer, the seed layer of the first wiring layer and the second wiring layer Each thickness of the seed layer is 1.0μm or more, a through electrode substrate.

  In addition, an embodiment of the present disclosure includes a substrate including a first surface and a second surface positioned on the opposite side of the first surface and provided with a through hole, and is disposed on the first surface and is electrically conductive. A first wiring layer having conductive properties, a second wiring layer located on the second surface and having conductivity, and a through electrode positioned in the through hole, wherein a side wall of the through hole has the first surface The taper is tapered over the second surface, and the angle formed between the side wall of the through hole and the normal direction of the substrate is 0.8 degrees or more, and the through electrode has the through hole Conformal vias provided on the sidewalls of the first and second wiring layers are electrically connected to each other, and the through electrode, the first wiring layer, and the second wiring layer are respectively A seed layer and a plating layer, the seed layer of the first wiring layer and the second wiring layer Each thickness of the seed layer is 1.5μm or more, a through electrode substrate.

  In the through electrode substrate according to an embodiment of the present disclosure, the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer may each be formed of a sputter layer.

  In the through electrode substrate according to the embodiment of the present disclosure, each thickness of the seed layer of the first wiring layer and the seed layer of the second wiring layer may be 3.0 μm or less.

  Further, in the through electrode substrate according to an embodiment of the present disclosure, an angle formed between a side wall of the through hole and a normal direction of the substrate may be 12 degrees or less.

  In the through electrode substrate according to the embodiment of the present disclosure, the thickness of the substrate may be not less than 300 μm and not more than 400 μm.

  In addition, an embodiment of the present disclosure includes a substrate including a first surface and a second surface positioned on the opposite side of the first surface and provided with a through hole, and is disposed on the first surface and is electrically conductive. A first wiring layer having conductivity, a second wiring layer having conductivity on the second surface, and a through electrode positioned in the through hole, wherein the side wall of the through hole has the first wiring layer A tapered first side wall portion that tapers from the surface toward the inner side of the substrate; and a tapered second side wall portion that tapers from the second surface toward the inner side of the substrate; An angle formed between each of the first sidewall portion and the second sidewall portion of the through hole and a normal direction of the substrate is 1.0 degree or more, and the through electrode is formed on the sidewall of the through hole. A conformal via provided to electrically connect the first wiring layer and the second wiring layer; Each of the through electrode, the first wiring layer, and the second wiring layer includes a seed layer and a plating layer, and each thickness of the seed layer of the first wiring layer and the seed layer of the second wiring layer is: A through electrode substrate having a thickness of 1.0 μm or more.

  In the through electrode substrate according to an embodiment of the present disclosure, the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer may each be formed of a sputter layer.

  In the through electrode substrate according to the embodiment of the present disclosure, each thickness of the seed layer of the first wiring layer and the seed layer of the second wiring layer may be 3.0 μm or less.

  In the through electrode substrate according to the embodiment of the present disclosure, an angle formed between the side wall of the through hole and the normal direction of the substrate may be 12 degrees or less.

  In the through electrode substrate according to the embodiment of the present disclosure, the thickness of the substrate may be not less than 300 μm and not more than 400 μm.

  According to the embodiment of the present disclosure, it is possible to efficiently manufacture a through electrode substrate that contributes to thinning of a device to be mounted.

It is sectional drawing which shows the penetration electrode board | substrate which concerns on one Embodiment. It is sectional drawing which expands and shows the penetration electrode of the penetration electrode board | substrate of FIG. It is a top view which shows the 1st surface 1st conductive layer of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is a figure which shows the manufacturing process of a penetration electrode substrate. It is sectional drawing which shows the penetration electrode board | substrate which concerns on other embodiment. It is sectional drawing which expands and shows the penetration electrode of the penetration electrode board | substrate of FIG. It is a figure which shows the manufacturing process of the penetration electrode substrate of FIG. It is a figure which shows the manufacturing process of the penetration electrode substrate of FIG. It is a figure which shows the manufacturing process of the penetration electrode substrate of FIG. It is sectional drawing of an example of the mounting substrate provided with a penetration electrode substrate and an element. It is a figure which shows the example of the product in which a penetration electrode substrate is mounted. It is a figure which shows the result of the experiment 1 which verified the relationship between the dimension condition of the through-hole of the board | substrate which comprises a through-electrode board | substrate, and the seed layer formed. It is a figure which shows the result of the experiment 2 which verified the relationship between the dimension condition of the through-hole of the board | substrate which comprises a through-electrode board | substrate, and the seed layer formed. It is a figure which shows the result of the experiment 3 which verified the relationship between the dimension condition of the through-hole of the board | substrate which comprises a through-electrode board | substrate, and the seed layer formed. It is a figure which shows the result of the experiment 4 which verified the relationship between the dimension condition of the through-hole of the board | substrate which comprises a through-electrode board | substrate, and the seed layer formed.

  Hereinafter, a through electrode substrate manufacturing method according to an embodiment of the present disclosure and a through electrode substrate manufactured by the manufacturing method will be described in detail with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in this specification, terms such as “substrate”, “base material”, “sheet”, and “film” are not distinguished from each other based only on the difference in names. For example, “substrate” and “base material” are concepts including members that can be called sheets and films. Furthermore, as used in this specification, the shape and geometric conditions and the degree thereof are specified. For example, terms such as “parallel” and “orthogonal”, length and angle values, and the like are bound to a strict meaning. Therefore, it should be interpreted including the extent to which similar functions can be expected. In the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference symbols or similar reference symbols, and repeated description thereof may be omitted. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

Through electrode substrate will be described below embodiments of the present disclosure. First, the configuration of the through electrode substrate 10 manufactured by the manufacturing method according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing the through electrode substrate 10.

  The through electrode substrate 10 includes a substrate 12, a through electrode 22, a first wiring structure unit 30, and a second wiring structure unit 40. Hereinafter, each component of the through electrode substrate 10 will be described.

(substrate)
The substrate 12 includes a first surface 13 and a second surface 14 located on the opposite side of the first surface 13. The substrate 12 is provided with a plurality of through holes 20 extending from the first surface 13 to the second surface 14.

The substrate 12 includes an inorganic material having a certain insulating property. For example, the substrate 12 is a glass substrate, quartz substrate, sapphire substrate, resin substrate, silicon substrate, silicon carbide substrate, alumina (Al ₂ O ₃ ) substrate, aluminum nitride (AlN) substrate, zirconium oxide (ZrO ₂ ) substrate, etc. Alternatively, these substrates are stacked. The substrate 12 may partially include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate.

  Examples of the glass used for the substrate 12 include non-alkali glass. The alkali-free glass is a glass that does not contain an alkali component such as sodium or potassium. The alkali-free glass includes, for example, boric acid instead of an alkali component. The alkali-free glass includes an alkaline earth metal oxide such as calcium oxide or barium oxide. Examples of the alkali-free glass include EN-A1 manufactured by Asahi Glass and Eagle XG manufactured by Corning. When the substrate 12 includes glass, the insulation of the substrate 12 can be improved. Thereby, when the capacitor 15 is formed by a part of the first wiring structure 30 as described later, the withstand voltage characteristic of the capacitor 15 can be enhanced.

  Moreover, when the board | substrate 12 contains glass, the thickness of the board | substrate 12 is 250 micrometers or more and 450 micrometers or less, for example. In particular, when the thickness of the substrate 12 is in the range of 300 μm or more and 400 μm or less, the desired through electrode substrate 10 can be reliably obtained by the manufacturing method according to this embodiment described later.

  In the example shown in FIG. 1, the through hole 20 formed in the substrate 12 has a tapered shape in which the side wall 21 is tapered from the first surface 13 to the second surface 14. More specifically, the through hole 20 in this example has a circular shape in plan view, and is tapered from the first surface 13 to the second surface 14. The taper shape means a “taper” when viewed globally, and the side wall 21 is linear in a cross-sectional view of the surface extending along the axial direction of the through hole 20 as shown in FIG. Even when the side wall 21 extends in a curved shape as a whole in this sectional view, includes a curved portion in part, or has a linear portion and a curved portion. If it is "taper" when viewed globally, these shapes are included in the concept of a taper shape.

  FIG. 2 shows an enlarged view of the through electrode 22 and also shows the through hole 20 in an enlarged manner. As shown in FIG. 2, the angle α formed between the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 is 1.0 degree or more. Although details will be described later, the present inventor ensures that the seed layer 221 of the through electrode 22 is formed on the side wall 21 of the through hole 20 by sputtering, vapor deposition, or a combination thereof by setting the angle α to 1.0 degree or more. We know that it can be formed. The through electrode 22 shown in FIGS. 1 and 2 grows a plating layer by setting the angle α of the through hole 20 to 1.0 degree or more and forming the seed layer 221 by sputtering, vapor deposition, or a combination thereof. A sufficient thickness of the seed layer 221 is ensured. Thereby, the penetration electrode 22 has the plating layer 222 which can ensure appropriate electroconductivity.

  The angle α is particularly preferably set in a range of 1.0 ° to 3.0 °. When the angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 is set in such an angle range, the proper formation of the seed layer 221 is ensured while the through hole 20 is formed. Since the radial dimension can be suppressed, the density of the through electrodes 22 can be improved.

  The length of the through hole 20, that is, the dimension of the through hole 20 in the normal direction of the first surface 13 is equal to the thickness of the substrate 12. Further, the width of the end portion on the large diameter side of the through hole 20, that is, the dimension S1 (see FIG. 4) in the in-plane direction of the first surface 13 of the end portion on the first surface 13 side is, for example, 40 μm or more and 150 μm or less. The width of the end portion on the small diameter side of the through hole 20, that is, the dimension S2 (see FIG. 4) in the in-plane direction of the second surface 14 at the end portion on the second surface 14 side is, for example, not less than 35 μm and not more than 145 μm. In consideration of manufacturing reliability and density of the through electrodes 22, the dimension S1 is preferably 70 μm or more and 100 μm or less, and the dimension S2 is preferably 45 μm or more and 85 μm or less, and the dimension S1 is 85 μm or more and 95 μm or less. It is particularly preferable that the dimension S2 is 70 μm or more and 85 μm or less. In addition, the ratio of the length to the width of the through hole 20, that is, the aspect ratio of the through hole 20 is, for example, 4 or more and 10 or less.

(Penetration electrode)
The through electrode 22 is a member that is located inside the through hole 20 and has conductivity. In the present embodiment, the thickness of the through electrode 22 is smaller than the width of the through hole 20, and therefore there is a space where the through electrode 22 does not exist inside the through hole 20. That is, the through electrode 22 is a so-called conformal via provided on the side wall 21 of the through hole 20. The thickness of the through electrode 22 is, for example, 100 nm or more and 20 μm or less.

  As described above, as shown in FIG. 2, the through electrode 22 includes the seed layer 221 and the plating layer 222 arranged in order from the side wall 21 side of the through hole 20 to the center side of the through hole 20.

  The seed layer 221 is a conductive layer that serves as a foundation for growing the plating layer 222 by depositing metal ions in the plating solution during the electroplating step of forming the plating layer 222 by electrolytic plating. is there. As a material for the seed layer 221, a conductive material such as copper, titanium, or a combination thereof can be used. The material of the seed layer 221 may be the same as or different from the material of the plating layer 222. The seed layer 221 has a thickness of 50 nm or more. The seed layer 221 is formed by a sputtering method, a vapor deposition method, or a combination of a sputtering method and a vapor deposition method. The vapor deposition method referred to here is specifically physical vapor deposition.

  The plating layer 222 is a conductive layer formed by plating. As a material constituting the plating layer 222, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, an alloy using these, or a laminate of these can be used. .

(First wiring structure)
Next, the first wiring structure unit 30 will be described. The first wiring structure portion 30 has layers such as a conductive layer and an insulating layer provided on the first surface 13 side so as to form an electric circuit on the first surface 13 side of the substrate 12. In the present embodiment, the capacitor 15 is configured by a part of the first wiring structure unit 30. A part of the inductor 16 is constituted by a part of the first wiring structure part 30. In the present embodiment, the first wiring structure unit 30 includes a first surface first conductive layer 31, a first surface first inorganic layer 32, a first surface second conductive layer 33, a first surface first organic layer 34, a first surface. The first-surface third conductive layer 35 and the first-surface second organic layer 36 are provided.

[First surface, first conductive layer]
The first surface first conductive layer 31 is a conductive layer located on the first surface 13 and functions as a first wiring layer. The first surface first conductive layer 31 may be electrically connected to the through electrode 22. In the illustrated example, the through electrode 22 is electrically connected to the first surface first conductive layer 31. . The first surface first conductive layer 31 includes a seed layer 221 and a plating layer 222 that are sequentially stacked on the first surface 13 of the substrate 12, similarly to the through electrode 22. The material constituting the first surface first conductive layer 31 is the same as the material constituting the through electrode 22. The seed layer 221 of the first surface first conductive layer 31 is formed at the same time as the seed layer 221 of the through electrode 22 and is formed by sputtering, vapor deposition, or a combination of sputtering and vapor deposition. Further, the plating layer 222 of the first surface first conductive layer 31 is formed simultaneously with the plating layer 222 of the through electrode 22.

  The thickness of the first surface first conductive layer 31 is, for example, not less than 1 μm and not more than 20 μm. Here, as described above, the inventors of the present invention set the angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 to 1.0 ° or more, so that sputtering, vapor deposition, or a combination thereof is performed. It has been found that the seed layer 221 of the through-electrode 22 can be reliably formed on the side wall 21 of the through-hole 20, but more specifically, the thickness of the seed layer 221 of the first conductive layer 31 on the first surface is 1 μm or more. Thus, by forming the seed layer 221 by sputtering or the like, the seed layer 221 of the through electrode 22 is reliably formed on the side wall 21 of the through hole 20. Therefore, in this embodiment, the thickness of the seed layer 221 of the first surface first conductive layer 31 is 1 μm or more. The thickness of the seed layer 221 in the first surface first conductive layer 31 is not less than 1 μm and not more than 5 μm, and preferably the seed layer 221 of the first surface first conductive layer 31 is in the range of not less than 1 μm and not more than 3.0 μm. By forming, the thickness of the 1st surface 1st conductive layer 31 can be made thin enough to contribute to thickness reduction of the penetration electrode substrate 10 enough.

[First surface, first inorganic layer]
The 1st surface 1st inorganic layer 32 is a layer which is located on the 1st surface 1st conductive layer 31 at least partially, contains an inorganic material, and has insulation. As the inorganic material of the first surface first inorganic layer 32, silicon nitride such as SiN can be used. Other examples of the inorganic material of the first surface first inorganic layer 32 include silicon oxide, aluminum oxide, and tantalum pentoxide. The relative dielectric constant of the inorganic material of the first surface first inorganic layer 32 is, for example, 3 or more and 50 or less. Moreover, the thickness of the 1st surface 1st inorganic layer 32 is 50 nm or more and 400 nm or less, for example. The first surface first inorganic layer 32 may be composed of a single layer or may include a plurality of layers.

[First surface, second conductive layer]
The first surface second conductive layer 33 is a conductive layer located on the first surface first inorganic layer 32. As shown in FIG. 1, the end portion 33 e of the first surface second conductive layer 33 is located on the first surface first inorganic layer 32. The first surface first conductive layer 31 described above, the first surface first inorganic layer 32 positioned on the first surface first conductive layer 31, and the first surface positioned on the first surface first inorganic layer 32. The capacitor 15 is configured by the surface second conductive layer 33.

  The first-surface second conductive layer 33 may include a seed layer and a plating layer that are sequentially stacked on the first-surface first inorganic layer 32, similarly to the through electrode 22 and the first-surface first conductive layer 31. Good. The material constituting the first surface second conductive layer 33 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 31. The thickness of the 1st surface 2nd conductive layer 33 is 100 nm or more and 20 micrometers or less, for example.

[First surface, first organic layer]
The 1st surface 1st organic layer 34 is a layer which is located on the 1st surface 1st inorganic layer 32 and the 1st surface 2nd conductive layer 33, contains an organic material, and has insulation. As the organic material of the first surface first organic layer 34, polyimide, epoxy, or the like can be used. The organic material of the first surface first organic layer 34 preferably has a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and still more preferably 0.001 or less. By configuring the first surface first organic layer 34 using an organic material having a small dielectric loss tangent, it is possible to suppress an electrical signal that should pass through the capacitor 15 and the inductor 16 from passing through the first surface first organic layer 34. be able to. Thereby, the band of the through electrode substrate 10 including the capacitor 15 and the inductor 16 can be expanded to the high frequency side.

[First surface, third conductive layer]
The first surface third conductive layer 35 is a conductive layer located on the first surface first conductive layer 31 or the first surface second conductive layer 33. In the example shown in FIG. 1, the first-surface third conductive layer 35 is a portion connected to the first-surface first conductive layer 31 that is one electrode of the capacitor 15 and the second electrode that is the other electrode of the capacitor 15. A portion connected to the first conductive layer 33 on the first surface is included.

  The first surface third conductive layer 35 may include a seed layer and a plating layer that are sequentially stacked, like the through electrode 22 and the first surface first conductive layer 31. The material constituting the first surface third conductive layer 35 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 31.

[First side, second organic layer]
The first surface second organic layer 36 is a layer that is located on the first surface first organic layer 34 and the first surface third conductive layer 35, includes an organic material, and has an insulating property. Like the first surface first organic layer 34, the first surface second organic layer 36 is preferably an organic material having a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and even more preferably 0.001 or less. Contains materials. As the organic material of the first surface second organic layer 36, as with the first surface first organic layer 34, polyimide, epoxy, or the like can be used.

(Second wiring structure)
Next, the second wiring structure unit 40 will be described. The second wiring structure unit 40 includes layers such as a conductive layer and an insulating layer provided on the second surface 14 side so as to form an electric circuit on the second surface 14 side of the substrate 12. The inductor 16 is configured by a part of the second wiring structure part 40, a part of the first wiring structure part 30 and the through electrode 22 described above. In the present embodiment, the second wiring structure unit 40 includes a second surface first conductive layer 41 and a second surface first organic layer 43.

[Second surface, first conductive layer]
The second surface first conductive layer 41 is a conductive layer located on the second surface 14 and functions as a second wiring layer. The second surface first conductive layer 41 may be connected to the through electrode 22. In the illustrated example, the through electrode 22 is connected to the second surface first conductive layer 41. The second surface first conductive layer 41 includes a seed layer 221 and a plating layer 222 that are sequentially stacked on the second surface 14 of the substrate 12, similarly to the through electrode 22 and the first surface first conductive layer 31. It is out. The material constituting the second surface first conductive layer 41 is the same as the material constituting the through electrode 22. The seed layer 221 of the second surface first conductive layer 41 is formed at the same time as the seed layer 221 of the through electrode 22 and is formed by sputtering, vapor deposition, or a combination of sputtering and vapor deposition. The plating layer 222 of the second surface first conductive layer 41 is formed simultaneously with the plating layer 222 of the through electrode 22.

  The thickness of the second surface first conductive layer 41 is, for example, not less than 1 μm and not more than 20 μm. Specifically, the thickness of the seed layer 221 of the second surface first conductive layer 41 is not less than 1 μm and not more than 5 μm, and preferably the seed layer 221 of the second surface first conductive layer 41 is in the range of not less than 1 μm and not more than 3 μm. By forming, the thickness of the 2nd surface 1st conductive layer 41 can be made thin to such an extent that it contributes enough to thickness reduction of the penetration electrode substrate 10. FIG. The formation of the seed layer 221 of the second surface first conductive layer 41 is performed at the same time as the seed layer 221 of the first surface first conductive layer 31 and is completed simultaneously. Therefore, the thickness of the seed layer 221 of the second surface first conductive layer 41 is basically the same as the thickness of the seed layer 221 of the first surface first conductive layer 31 and is 1 μm or more.

  FIG. 3 is a plan view showing a case where the first surface first conductive layer 31 and the second surface first conductive layer 41 of the through electrode substrate 10 are viewed from the first surface 13 side. In FIG. 3, layers such as the first surface first inorganic layer 32 laminated on the first surface first conductive layer 31 are omitted. In FIG. 3, the second surface first conductive layer 41 located on the second surface 14 side is represented by a dotted line. As shown in FIGS. 1 and 3, the second-surface first conductive layer 41, the through-electrode 22 connected to the second-surface first conductive layer 41, and the first-surface first conductivity connected to the through-electrode 22. The inductor 31 is constituted by the layer 31.

[Second side, first organic layer]
The 2nd surface 1st organic layer 43 is a layer which is located on the 2nd surface 1st conductive layer 41, contains an organic material, and has insulation. Similarly to the first surface first organic layer 34 and the first surface second organic layer 36, the second surface first organic layer 43 is preferably 0.003 or less, more preferably 0.002 or less, and still more preferably 0. Organic materials having a dielectric loss tangent of .001 or less are included. As the organic material of the second surface first organic layer 43, polyimide, epoxy, or the like can be used as in the first surface first organic layer 34 and the first surface second organic layer 36.

Method for producing a through electrode substrate Hereinafter, an example of a manufacturing method of the through electrode substrate 10 described above will be described with reference to FIGS 12.

(Through hole forming process)
First, the substrate 12 is prepared. Next, a resist layer is provided on at least one of the first surface 13 and the second surface 14. Thereafter, an opening is provided at a position corresponding to the through hole 20 in the resist layer. Next, by processing the substrate 12 in the opening of the resist layer, the through hole 20 can be formed in the substrate 12 as shown in FIG. As a method for processing the substrate 12, a dry etching method such as a reactive ion etching method or a deep reactive ion etching method, a wet etching method, or the like can be used.

  The through hole 20 may be formed in the substrate 12 by irradiating the substrate 12 with a laser. In this case, the resist layer may not be provided. As a laser for laser processing, an excimer laser, an Nd: YAG laser, a femtosecond laser, or the like can be used. When an Nd: YAG laser is employed, a fundamental wave having a wavelength of 1064 nm, a second harmonic having a wavelength of 532 nm, a third harmonic having a wavelength of 355 nm, or the like can be used.

  Further, laser irradiation and wet etching can be appropriately combined. Specifically, first, a deteriorated layer is formed in a region of the substrate 12 where the through hole 20 is to be formed by laser irradiation. Subsequently, the altered layer is etched by immersing the substrate 12 in hydrogen fluoride or the like. Thereby, the through hole 20 can be formed in the substrate 12. In addition, the through holes 20 may be formed in the substrate 12 by a blasting process in which an abrasive is sprayed onto the substrate 12.

For example, by processing the substrate 12 only from the first surface 13 side, the through-hole 20 having a shape that decreases in width from the first surface 13 side to the second surface 14 side of the substrate 12 shown in FIG. 4 is formed. can do. Here, in the manufacturing method according to the present embodiment, the angle α formed between the side wall 21 of the through hole 20 of the substrate 12 and the normal direction nd of the substrate 12 is set to 1.0 ° or more.
(Penetration electrode formation process)
Next, the through electrode 22 is formed on the side wall 21 of the through hole 20. In the present embodiment, the first surface first conductive layer 31 is formed on a portion of the first surface 13 and the second surface first conductive layer 41 is formed on a portion of the second surface 14 simultaneously with the through electrode 22. Is done.

  As shown in FIG. 5, the seed layer 221 is formed on the first surface 13, the second surface 14, and the side wall 21 of the through hole 20 by sputtering, vapor deposition, or a combination thereof. Here, in this embodiment, the angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 is set to 1.0 ° or more, and then the seed layer of the first conductive layer 31 on the first surface is formed. The seed layer 221 of the first surface first conductive layer 31 is formed so that the thickness of 221 is 1 μm or more. As a result, the seed layer 221 of the through electrode 22 is reliably formed on the side wall 21 of the through hole 20. Subsequently, as shown in FIG. 6, a resist layer 37 is partially formed on the seed layer 221. Subsequently, as illustrated in FIG. 7, a plating layer 222 is formed on the seed layer 221 not covered with the resist layer 37 by electrolytic plating. Thereafter, as shown in FIG. 8, the resist layer 37 is removed. Further, the portion of the seed layer 221 that is covered with the resist layer 37 is removed by, for example, wet etching. In this way, the through electrode 22, the first surface first conductive layer 31, and the second surface first conductive layer 41 can be formed. Thus, the inductor 16 including the second surface first conductive layer 41, the through electrode 22 connected to the second surface first conductive layer 41, and the first surface first conductive layer 31 connected to the through electrode 22. Can be configured. Note that a step of annealing the plating layer 222 may be performed.

(Formation process of 1st surface 1st inorganic layer)
Next, as shown in FIG. 9, the first surface first inorganic layer 32 is formed over the entire area of the first surface first conductive layer 31. As a method of forming the first surface first inorganic layer 32, for example, plasma CVD, sputtering, or the like can be employed. Preferably, the process of forming the 1st surface 1st inorganic layer 32 is continuously implemented in the same apparatus as the case of the process of forming the 1st surface 1st conductive layer 31, and the surface treatment process. These steps are preferably performed in an atmosphere in which the first surface first conductive layer 31 is suppressed from being oxidized, for example, in an atmosphere of a reducing gas such as ammonia gas.

(Formation process of 1st surface 2nd conductive layer)
Next, as shown in FIG. 10, the first surface second conductive layer 33 is formed on a part of the first surface first inorganic layer 32. Thus, the first surface first conductive layer 31, the first surface first inorganic layer 32 on the first surface first conductive layer 31, and the first surface second conductive layer on the first surface first inorganic layer 32. 33 can be configured. Since the process of forming the 1st surface 2nd conductive layer 33 is the same as the process of forming the 1st surface 1st conductive layer 31, description is abbreviate | omitted.

(Formation process of 1st surface 1st organic layer)
Next, as shown in FIG. 11, the first surface first organic layer 34 is formed on a portion of the first surface second conductive layer 33 and on a portion of the first surface first inorganic layer 32. For example, first, a first surface side film having a photosensitive layer containing an organic material and a base material is attached to the first surface 13 side of the substrate 12. Subsequently, the first surface side film is subjected to exposure processing and development processing. Accordingly, the first surface first organic layer 34 made of the photosensitive layer of the first surface side film and having the opening 34 a formed thereon can be formed on the first surface 13 side of the substrate 12. At this time, in the same manner as in the case of the first surface first organic layer 34, as shown in FIG. 11, the second surface first on the second surface 14 and on the second surface first conductive layer 41. The organic layer 43 may be formed.

  The opening 34a of the first surface first organic layer 34 is a position where the first surface third conductive layer 35 and the first surface first conductive layer 31 are connected, the first surface third conductive layer 35 and the first surface. It is formed on the first surface first inorganic layer 32 at a position where the second conductive layer 33 is connected.

  In addition, the formation method of the 1st surface 1st organic layer 34 and the 2nd surface 1st organic layer 43 is not restricted to the method using a film. For example, first, a liquid containing an organic material such as polyimide is applied by a spin coating method or the like, and dried to form an organic layer. Then, the 1st surface 1st organic layer 34 and the 2nd surface 1st organic layer 43 can also be formed by performing an exposure process and a development process to an organic layer.

(First surface third conductive layer forming step)
Next, as shown in FIG. 12, the first surface connected to the first surface first conductive layer 31 or the first surface second conductive layer 33 through the opening 34 a of the first surface first organic layer 34. Three conductive layers 35 are formed. Since the process of forming the 1st surface 3rd conductive layer 35 is the same as the process of forming the 1st surface 1st conductive layer 31, description is abbreviate | omitted.

(First surface second organic layer forming step)
Thereafter, a first surface second organic layer 36 is formed on a portion of the first surface first organic layer 34 and on a portion of the first surface third conductive layer 35. Thereby, the through electrode substrate 10 shown in FIG. 1 can be obtained. The method for forming the first surface second organic layer 36 is not particularly limited. For example, as in the case of the first surface first organic layer 34, the first surface second organic layer 36 can be formed by using a film or liquid containing an organic material.

By the way, the present inventor sets the angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 to 1.0 ° or more, and the first surface 1 is formed by sputtering or vapor deposition. By forming the seed layer 221 so that the thickness of the seed layer 221 of the conductive layer 31 is 1 μm or more, the seed layer 221 of the through electrode 22 can be reliably formed on the side wall 21 of the through hole 20. Knowing and creating the above manufacturing procedure.

  Here, FIG.20 and FIG.21 has shown the experimental result which became the opportunity for this inventor to acquire the above-mentioned knowledge. FIG. 20 is a diagram showing the results of Experiment 1 in which the relationship between the dimensional conditions of the through holes of the substrate constituting the through electrode substrate and the seed layer to be formed is verified. It is a figure which shows the experimental result which verified whether the seed layer was formed in the side wall of a through-hole by performing sputtering by setting these dimension conditions, and this sputtering. FIG. 21 is a diagram showing the result of Experiment 2 in which the relationship between the dimensional condition of the through hole of the substrate constituting the through electrode substrate and the seed layer to be formed is verified, and the through hole in the substrate having a thickness of 300 μm It is a figure which shows the experimental result which verified whether the seed layer was formed in the side wall of a through-hole by performing sputtering, setting various dimensional conditions to this. In each experiment, the through hole has a tapered shape as shown in FIG.

  In the table portion shown in FIG. 20 and FIG. 21A, various dimensional conditions of the through holes are shown. In the front portion of (A), “Top” indicates a width dimension corresponding to the width dimension of the end portion on the first surface 13 side of the through hole 20 shown in FIG. 1, and “Bottom” indicates the first dimension of the through hole 20. The width dimension corresponding to the width dimension of the edge part on the 2nd surface 14 side is shown. “T−B / 2” indicates a value obtained by subtracting a width dimension of “Bottom” from a width dimension of “Top” and dividing by 2, and “tan” indicates a value of “T−B / 2” of the substrate. The value divided by the thickness dimension is shown. “Deg” indicates an angle between the side wall of the through hole and the normal direction of the substrate, which is calculated based on “tan”.

  20 and 21, the front portion indicated by (B) is a through hole when the seed layer is formed under various thickness conditions on the surface of the substrate having various dimensional conditions of the through hole indicated by (A). The formation result of the plating layer in the side wall is shown. Specifically, the thickness of the seed layer is 0.5 μm, 0.7 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm on the surface of the substrate having through holes of various dimensional conditions. The result of adhesion of the plating layer to the seed layer on the side wall of the through hole when the seed layer is formed to be 0 μm is shown. 20 and FIG. 21 indicate that the plated layer is attached in the region with dots, and that the plated layer is not attached in the other regions. In FIG. 20 and FIG. 21B, when the seed layer having a thickness of 1.0 μm and 1.5 μm is formed on the surface of the substrate, the minimum adhesion of the plating layer to the side wall of the through hole is confirmed. A dark dot is attached to a region corresponding to the dimensional condition of the angle.

  Experiment 1 in FIG. 20 is an experimental result when a plating layer is formed after a seed layer is formed on a substrate having a through hole with a “Top” width of 85 μm, 90 μm, and 95 μm. In Experiment 1, when a seed layer having a thickness of 1.0 μm is formed on the substrate surface, the minimum angle at which the plating layer is confirmed to adhere to the side wall of the through hole is 1 regardless of the width dimension of “Top”. 0.092 degrees (deg). Further, Experiment 2 in FIG. 21 is an experiment in which a plating layer is formed after forming a seed layer on a substrate having a through-hole whose “Top” width is 75 μm, 80 μm, 85 μm, 90 μm, and 95 μm. It is a result. In this experiment 2, when a seed layer having a thickness of 1.0 μm is formed on the substrate surface, the minimum angle at which the plating layer is confirmed to adhere to the side wall of the through hole is 1 regardless of the width dimension of “Top”. .1724 degrees (deg).

  Based on the experimental results as described above, the inventor forms a seed layer having a thickness of 1.0 μm with the angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 being approximately 1.0 degrees. It has been found that if the surface of the substrate 12 is formed by sputtering, a seed layer 221 is formed on the side wall 21 of the through hole 20 to such an extent that the plating layer is sufficiently grown. That is, it can be seen that the seed layer 221 is formed when the plating layer 222 is formed. Based on this knowledge, in the step of forming the seed layer described with reference to FIG. 5, the angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 is 1.0 degree or more, Then, the seed layer 221 of the first surface first conductive layer 31 is formed so that the thickness of the seed layer 221 of the first surface first conductive layer 31 is 1 μm or more, whereby the seed layer of the through electrode 22 is formed. The 221 is reliably formed on the side wall 21 of the through hole 20. When the angle α is 1.1 degrees or more and 1.2 degrees or more, the seed layer can be formed more sufficiently.

20 and 21, the example in which the seed layer is formed by sputtering has been described. However, the angle α formed between the side wall 21 of the through-hole 20 and the normal direction nd of the substrate 12 is set to 1.0 ° or more, and a seed layer having a thickness of 1.0 μm is deposited on the surface of the substrate 12, or sputtering and deposition are performed. The present inventor has confirmed that the seed layer 221 is formed on the side wall 21 of the through-hole 20 so that the plating layer is sufficiently grown even when formed by a combination. It should be noted that since the deposition is smaller in the movement direction of the metal particles to be adhered than the sputtering, it is assumed that the seed layer adheres to the sidewall more easily than the sputtering if the angle α is the same. Is done. Note that when the seed layer is formed by sputtering, the density of the seed layer is higher than the density of the seed layer formed by vapor deposition, which is advantageous in that high conductivity can be secured. Further, the surface roughness of the seed layer formed by sputtering is smaller than the surface roughness of the seed layer formed by vapor deposition. In addition, the adhesion of the seed layer formed by sputtering to the side wall 21 is higher than the adhesion of the seed layer formed by vapor deposition to the side wall 21.
Whether the seed layer is a layer formed by sputtering (hereinafter also referred to as a sputtered layer) or a layer formed by vapor deposition (hereinafter also referred to as a deposited layer) is determined based on, for example, the surface roughness of the seed layer. be able to. For example, the surface roughness of the sputter layer is 0.05 μm or less, and the surface roughness of the vapor deposition layer is greater than 0.1 μm. As an index of surface roughness, for example, arithmetic average roughness defined in JIS B 0601: 2001 can be adopted.

  As described above, in the method of manufacturing the through electrode substrate according to the present embodiment, first, the first surface 13 and the second surface 14 located on the opposite side of the first surface 13 are included and the through hole 20 is provided. In the substrate 12, the side wall 21 of the through hole 20 is tapered from the first surface 13 to the second surface 14, and the side wall 21 of the through hole 20 and the normal direction of the substrate 12 form. A substrate 12 having an angle of 1.0 degree or more is prepared. Next, a seed layer 221 is formed on the first surface 13, the second surface 14, and the through hole 20 of the substrate 12 by sputtering. Next, by forming a plating layer 222 on the seed layer 221, the first surface first conductive layer 31 located on the first surface 13 and the second surface first conductive layer 41 located on the second surface 14. And the penetration electrode 22 located in the through-hole 20 is formed. Then, in the step of forming the seed layer, each seed layer 221 is formed such that the thickness of the seed layer of the first surface first conductive layer 31 and the seed layer of the second surface first conductive layer 41 is 1.0 μm or more. And a seed layer 221 of the through electrode 22 is formed on the side wall 21 of the through hole 20.

  Thereby, the through electrode substrate 10 that contributes to the thinning of the device to be mounted can be efficiently manufactured. That is, according to the manufacturing method according to the present embodiment, if each seed layer 221 is formed so that the thickness of the seed layer of the first surface first conductive layer 31 is at least 1.0 μm, appropriate conductivity can be obtained. The secured through electrode substrate 10 can be manufactured. Therefore, by arbitrarily suppressing the thickness of the seed layer of the first conductive layer 31 on the first surface, it is possible to manufacture the through electrode substrate 10 that is thinned as desired and has appropriate conductivity while suppressing the material. It becomes possible. As a result, the through electrode substrate 10 that contributes to the thinning of the device to be mounted can be efficiently manufactured.

(Modification 1)
In the method of manufacturing the through electrode substrate according to Modification 1, the through electrode substrate 10 having a through hole that is tapered from the first surface 13 to the second surface 14 is formed in the same manner as the through electrode substrate shown in FIG. It is a method to do. The modification 1 is demonstrated using the code | symbol used in the above-mentioned embodiment.

  In the method according to the first modification, first, the substrate 12 includes the first surface 13 and the second surface 14 located on the opposite side of the first surface 13 and is provided with the through hole 20. The side wall 21 is tapered from the first surface 13 to the second surface 14, and the angle α formed by the side wall 21 of the through hole 20 and the normal direction of the substrate 12 is 0.8 degrees or more. A substrate 12 is prepared.

  Next, a seed layer 221 is formed on the first surface 13, the second surface 14, and the through hole 20 of the substrate 12 by sputtering, vapor deposition, or a combination thereof. Next, by forming a plating layer 222 on the seed layer 221, the first surface first conductive layer 31 located on the first surface 13 and the second surface first conductive layer 41 located on the second surface 14. And the penetration electrode 22 located in the through-hole 20 is formed. Here, in the first modification, in the step of forming the seed layer, each thickness of the seed layer of the first surface first conductive layer 31 and the seed layer of the second surface first conductive layer 41 is 1.5 μm or more. As described above, each seed layer 221 is formed, and the seed layer 221 of the through electrode 22 is formed on the side wall 21 of the through hole 20.

  Experiment 1 in FIG. 20 described above shows the experimental results when a seed layer is formed and then a plating layer is formed on a substrate having a through hole with a “Top” width of 85 μm, 90 μm, and 95 μm. ing. In Experiment 1, when a 1.5 μm thick seed layer was formed on the substrate surface, the minimum angle at which the plating layer was confirmed to adhere to the side wall of the through hole was 0 regardless of the width dimension of “Top”. It is 8794 degrees (deg). Further, in Experiment 1 of FIG. 21, an experiment in which a plating layer is formed after a seed layer is formed on a substrate having a through hole with a “Top” width of 75 μm, 80 μm, 85 μm, 90 μm, and 95 μm. Results are shown. In this experiment 2, when a seed layer having a thickness of 1.5 μm is formed on the substrate surface, the minimum angle at which the plating layer is confirmed to adhere to the side wall of the through hole is 0 regardless of the width dimension of “Top”. 7817 degrees (deg).

  Based on the experimental results as described above, the present inventors set a seed layer having a thickness of 1.5 μm with an angle α formed by the side wall 21 of the through hole 20 and the normal direction nd of the substrate 12 being approximately 0.80 degrees. It has been found that if the surface of the substrate 12 is formed by sputtering, a seed layer 221 is formed on the side wall 21 of the through hole 20 to such an extent that the plating layer is sufficiently grown. The manufacturing method which concerns on the modification 1 is created based on such knowledge.

(Other embodiments)
Next, a method for manufacturing a through electrode substrate according to another embodiment will be described with reference to FIGS. The same components as those in the above-described embodiment are denoted by the same reference numerals, and the following description will be given.

  13 and 14 show the through electrode substrate 10 manufactured by the manufacturing method according to the present embodiment. As shown in these drawings, in the through electrode substrate 10, the side wall 21 of the through hole 20 tapers from the first surface 13 toward the inner side of the substrate 12, and the tapered first side wall portion 21 </ b> A, And a tapered second side wall portion 21B that tapers from the second surface 14 toward the inside of the substrate 12.

  More specifically, the first side wall portion 21 </ b> A in this example has a circular shape in plan view, and has a tapered shape that tapers from the first surface 13 toward the second surface 14. The second side wall portion 21 </ b> B has a circular shape in plan view, and has a tapered shape that tapers from the second surface 14 toward the first surface 13. The first side wall portion 21 </ b> A and the second side wall portion 21 </ b> B are coupled to each other at the center in the thickness direction of the substrate 12. Note that the taper shape means “taper” when viewed globally, and the first side wall portion 21A in a cross-sectional view of the surface extending along the axial direction of the through hole 20 as shown in FIG. In addition, the first side wall 21A and the second side wall 21B are not limited to a mode in which the second side wall 21B extends linearly. Even in the case of including a straight part and a curved part, these shapes are included in the concept of a taper as long as they are “tapered” as a whole.

  Further, as shown in FIG. 14, the angle α formed by each of the first side wall portion 21A and the second side wall portion 21B of the through hole 20 and the normal direction nd of the substrate 12 is 1.0 degree or more. . Although details will be described later, the present inventor ensures that the seed layer 221 of the through electrode 22 is formed on the side wall 21 of the through hole 20 by sputtering, vapor deposition, or a combination thereof by setting the angle α to 1.0 degree or more. We know that it can be formed. The through electrode 22 shown in FIG. 14 has an angle α of the through hole 20 of 1.0 degree or more, and the seed layer 221 is formed by sputtering, vapor deposition, or a combination thereof, which is sufficient for growing a plating layer. The thickness of the seed layer 221 is ensured. Thereby, the penetration electrode 22 has the plating layer 222 which can ensure appropriate electroconductivity.

  The angle α is particularly preferably set in a range of 1.0 ° to 3.0 °. When the angle α formed by the first sidewall portion 21A and the second sidewall portion 21B and the normal direction nd of the substrate 12 is set in such an angle range, the proper formation of the seed layer 221 is ensured. However, since the size of the through hole 20 in the radial direction can be suppressed, the density of the through electrodes 22 can be improved.

  The length of the through hole 20, that is, the dimension of the through hole 20 in the normal direction of the first surface 13 is equal to the thickness of the substrate 12. Further, the width of the end portion of the through hole 20 on the large diameter side, that is, the dimension S1 ′ in the in-plane direction of the first surface 13 or the second surface 14 at both end portions on the first surface 13 and second surface 14 side (see FIG. 15). ) Is, for example, 40 μm or more and 150 μm or less. Further, the width of the coupling portion of the first side wall portion 21A and the second side wall portion 21B, that is, the dimension S2 ′ (see FIG. 15) in the in-plane direction of the first surface 13 or the second surface 14 of the coupling portion is, for example, 20 μm or more and 130 μm or less. In consideration of manufacturing reliability and the density of the through electrodes 22, it is preferable that the dimension method S <b> 1 ′ is 70 μm to 100 μm and the dimension S <b> 2 ′ is 45 μm to 90 μm. In addition, the ratio of the length to the width of the through hole 20, that is, the aspect ratio of the through hole 20 is, for example, 4 or more and 10 or less. In addition, although it is preferable that the connection part of 21 A of 1st side wall parts and the 2nd side wall part 21B is formed in the center of the thickness direction of the board | substrate 12, you may offset from the center.

  Other components in the through electrode substrate 10 are the same as those in the above-described embodiment.

  When manufacturing the through electrode substrate 10 in the present embodiment, first, as shown in FIG. 15, each of the first side wall portion 21 </ b> A and the second side wall portion 21 </ b> B of the through hole 20 of the substrate 12 and the method of the substrate 12. A substrate 12 is prepared in which an angle α formed by the line direction nd is 1.0 degree or more.

  Next, the through electrode 22 is formed on the side wall 21 of the through hole 20. In the present embodiment, the first surface first conductive layer 31 is formed on a portion of the first surface 13 and the second surface first conductive layer 41 is formed on a portion of the second surface 14 simultaneously with the through electrode 22. Is done.

  As shown in FIG. 16, a seed layer 221 is formed on the first surface 13, the second surface 14, and the sidewall 21 of the through hole 20 by sputtering, vapor deposition, or a combination thereof. Here, in the present embodiment, an angle α formed by each of the first side wall portion 21A and the second side wall portion 21B of the through hole 20 and the normal direction nd of the substrate 12 is 1.0 degree or more, Thus, each seed layer 221 is formed such that the seed layer 221 of the first surface first conductive layer 31 and the seed layer 221 of the second surface first conductive layer 41 have a thickness of 1 μm or more. As a result, the seed layer 221 of the through electrode 22 is reliably formed on the side wall 21 of the through hole 20. Subsequently, after forming a resist layer (not shown) at a desired position, a plating layer 222 is formed, and then the resist layer is removed, and a portion covered with the resist layer is removed by, for example, wet etching. In this way, as shown in FIG. 17, the through electrode 22, the first surface first conductive layer 31, and the second surface first conductive layer 41 can be formed.

  The details of the conditions at the time of forming the seed layer will be described below. FIGS. 22 and 23 show experimental results that led the inventors to reach the manufacturing method according to the other embodiment described above. FIG. 22 is a diagram showing the result of Experiment 3 in which the relationship between the dimensional condition of the through hole of the substrate constituting the through electrode substrate and the seed layer to be formed is verified. In the substrate having a thickness of 400 μm, various through holes are shown. It is a figure which shows the experimental result which verified whether the seed layer was formed in the side wall of a through-hole by sputtering, setting the dimension conditions of this. FIG. 23 is a diagram showing the results of Experiment 4 in which the relationship between the dimensional conditions of the through-holes of the substrate constituting the through-electrode substrate and the seed layer to be formed is verified. In the substrate having a thickness of 300 μm, It is a figure which shows the experimental result which verified whether the seed layer was formed in the side wall of a through-hole by sputtering, setting various dimension conditions to this. In each experiment, the through hole has an hourglass shape as shown in FIG.

  In the table portion shown in FIG. 22 and FIG. 23A, various dimensional conditions of the through holes are shown. In the front part of (A), “Top” indicates a width dimension corresponding to the width dimension of the end portions on the first surface 13 side and the second surface 14 side of the through-hole 20 shown in FIG. 14, and “Middle” The width dimension corresponding to the width dimension of the coupling | bond part of 21 A of 1st side wall parts and the 2nd side wall part 21B is shown. “TM / 2” indicates a value obtained by subtracting the width dimension of “Middle” from the width dimension of “Top” and dividing by 2, and “tan” indicates the value of “TM / 2” of the substrate. The value divided by the thickness dimension is shown. “Deg” represents an angle formed by each of the first side wall portion and the second side wall portion of the through hole and the normal direction of the substrate, which is calculated based on “tan”.

  In FIG. 22 and FIG. 23, the front portion shown by (B) is the through hole when the seed layer is formed on the surface of the substrate having various dimensional conditions of the through hole shown by (A) under various thickness conditions. The formation result of the plating layer in the side wall is shown. Specifically, the thickness of the seed layer is 0.5 μm, 0.7 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm on the surface of the substrate having through holes of various dimensional conditions. The result of adhesion of the plating layer to the seed layer on the side wall of the through hole when the seed layer is formed to be 0 μm is shown. In FIG. 22 and FIG. 23, the region marked with dots indicates that the plating layer has adhered, and the other regions indicate that the plating layer has not adhered. In FIG. 22 and FIG. 23B, when the seed layer having a thickness of 1.0 μm is formed on the surface of the substrate, the dimensional condition of the minimum angle in which the adhesion of the plating layer to the side wall of the through hole is confirmed. A dark dot is attached to the corresponding area.

  Experiment 3 in FIG. 22 is an experimental result when a plating layer is formed after a seed layer is formed on a substrate having a through hole with a width dimension of “Top” of 85 μm, 90 μm, and 95 μm. In Experiment 3, when a seed layer having a thickness of 1.0 μm was formed on the substrate surface, the minimum angle at which the plating layer was confirmed to adhere to the side wall of the through hole was 1.0259 when the through hole diameter was 85 μm. When the through hole diameter is 90 μm, it is 1.1724 degrees (deg), and when the through hole diameter is 95 μm, it is 1.1724 degrees (deg). Experiment 4 in FIG. 23 is an experiment in which a plating layer is formed after forming a seed layer on a substrate having a through hole with a “Top” width of 75 μm, 80 μm, 85 μm, 90 μm, and 95 μm. It is a result. In Experiment 4, when a seed layer having a thickness of 1.0 μm is formed on the substrate surface, the minimum angle at which the plating layer is confirmed to adhere to the side wall of the through hole is 1.3678 when the through hole diameter is 75 μm. When the through hole diameter is 80 μm, it becomes 1.1724 degrees (deg), when the through hole diameter is 85 μm, it becomes 1.3678 degrees (deg), and when the through hole diameter is 90 μm, When the through-hole diameter is 95 μm, it is 1.3678 degrees (deg).

  Based on the above experimental results, the present inventor sets the angle α formed by the first side wall portion 21A and the second side wall portion 21B of the through hole 20 and the normal direction nd of the substrate 12 to approximately 1.0. As a result, it was found that if a seed layer having a thickness of 1.0 μm is formed on the surface of the substrate 12 by sputtering, the seed layer 221 is formed on the side wall 21 of the through hole 20 so that the plating layer is sufficiently grown. . That is, it can be seen that the seed layer 221 is formed when the plating layer 222 is formed. Based on this knowledge, in the step of forming the seed layer described with reference to FIG. 16, the first side wall portion 21 </ b> A and the second side wall portion 21 </ b> B of the through hole 20 of the through hole 20 and the normal direction of the substrate 12 The angle α formed by nd is set to 1.0 ° or more, and then the thickness of each seed layer 221 of the first surface first conductive layer 31 and the second surface first conductive layer 41 is 1 μm or more. By forming each seed layer 221, the seed layer 221 of the through electrode 22 is reliably formed on the side wall 21 of the through hole 20. If the angle α is 1.1 degrees or more, 1.2 degrees or more, 1.3 degrees or more, 1.4 degrees or more, the seed layer can be formed more sufficiently.

  Note that FIGS. 22 and 23 illustrate an example in which the seed layer is formed by sputtering. However, even when a seed layer having a thickness of 1.0 μm is formed on the surface of the substrate 12 by vapor deposition or by a combination of sputtering and vapor deposition, the present inventor believes that the seed layer 221 is formed on the side wall 21 of the through hole 20. I have confirmed. It should be noted that since the deposition is smaller in the movement direction of the metal particles to be adhered than the sputtering, it is assumed that the seed layer adheres to the sidewall more easily than the sputtering if the angle α is the same. Is done. Note that when the seed layer is formed by sputtering, the density of the seed layer is higher than that of vapor deposition, which is advantageous in that high conductivity can be secured.

  As described above, the through electrode substrate 10 that contributes to the thinning of the device to be mounted can also be efficiently manufactured by the method for manufacturing the through electrode substrate according to the present embodiment. That is, according to the manufacturing method according to the present embodiment, each thickness of the seed layer of the first surface first conductive layer 31 and the seed layer of the second surface first conductive layer 41 is at least 1.0 μm. By forming the seed layer 221, it is possible to manufacture the through electrode substrate 10 that ensures appropriate conductivity. For this reason, the thickness of the seed layer of the first conductive layer 31 on the first surface and the seed layer of the first conductive layer 41 on the second surface is arbitrarily suppressed, thereby reducing the thickness as desired and ensuring proper conductivity. The electrode substrate 10 can be manufactured while suppressing the material. As a result, the through electrode substrate 10 that contributes to the thinning of the device to be mounted can be efficiently manufactured.

(Mounting board)
FIG. 18 is a cross-sectional view showing an example of a mounting substrate 60 including a through electrode substrate 10 and an element 61 mounted on the through electrode substrate 10 and electrically connected to the through electrode 22 provided in the through hole 20. It is. The element 61 is an LSI chip such as a logic IC or a memory IC. The element 61 may be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic device in which mechanical element parts, sensors, actuators, electronic circuits, and the like are integrated on a single substrate. As shown in FIG. 18, the element 61 has a terminal 62 electrically connected to a conductive layer such as the first conductive layer 35 on the first surface of the through electrode substrate 10.

FIG. 19 is a diagram illustrating an example of a product on which the through electrode substrate 10 according to the embodiment of the present disclosure can be mounted. The through electrode substrate 10 according to the embodiment of the present disclosure can be used in various products. For example, it is mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

DESCRIPTION OF SYMBOLS 10 ... Through-electrode board | substrate 12 ... Board | substrate 13 ... 1st surface 14 ... 2nd surface 20 ... Through-hole 21 ... Side wall 21A ... 1st side wall part 21B ... 2nd side wall part 22 ... Through-hole electrode 221 ... Seed layer 222 ... Plating layer 22 … Through electrode nd… normal direction

Claims (22)

A substrate including a first surface and a second surface located on the opposite side of the first surface and provided with a through hole, wherein a side wall of the through hole is tapered from the first surface to the second surface. A step of preparing a substrate having a tapered shape, and an angle formed between a side wall of the through hole and a normal direction of the substrate is 1.0 degree or more;
Forming a seed layer on the first surface, the second surface and the through hole of the substrate using at least one of physical vapor deposition and sputtering;
By forming a plating layer on the seed layer, a first wiring layer located on the first surface and having conductivity, and a second wiring layer located on the second surface and having conductivity. Forming a through electrode located in the through hole, and
In the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the first wiring layer are formed so that the thickness of the seed layer of the first wiring layer and the seed layer of the second wiring layer is 1.0 μm or more. A method of manufacturing a through electrode substrate, wherein a seed layer of two wiring layers is formed and a seed layer of the through electrode is formed on a side wall of the through hole. A substrate including a first surface and a second surface located on the opposite side of the first surface and provided with a through hole, wherein a side wall of the through hole is tapered from the first surface to the second surface. A step of preparing a substrate that is tapered, and an angle formed between a side wall of the through hole and a normal direction of the substrate is 0.8 degrees or more;
Forming a seed layer on the first surface, the second surface and the through hole of the substrate using at least one of physical vapor deposition and sputtering;
By forming a plating layer on the seed layer, a first wiring layer located on the first surface and having conductivity, and a second wiring layer located on the second surface and having conductivity. Forming a through electrode located in the through hole, and
In the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the first wiring layer are formed so that each thickness of the seed layer of the first wiring layer and the seed layer of the second wiring layer is 1.5 μm or more. A method of manufacturing a through electrode substrate, wherein a seed layer of two wiring layers is formed and a seed layer of the through electrode is formed on a side wall of the through hole.   2. The method of manufacturing a through electrode substrate according to claim 1, wherein the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer are each formed by sputtering.   4. The method according to claim 1, wherein in the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the second wiring layer are formed in a thickness range of 3.0 μm or less. A method of manufacturing a through electrode substrate.   The through electrode substrate manufacturing method according to claim 1, wherein an angle formed between a side wall of the through hole and a normal direction of the substrate is 12 degrees or less.   The method for manufacturing a through electrode substrate according to claim 1, wherein the thickness of the substrate is 300 μm or more and 400 μm or less. A substrate including a first surface and a second surface located on the opposite side of the first surface and provided with a through hole, wherein a side wall of the through hole is directed from the first surface toward the inner side of the substrate. A tapered first side wall portion tapered and a tapered second side wall portion tapered from the second surface toward the inner side of the substrate; and the first side wall portion of the through hole. And a step of preparing a substrate in which an angle formed between each of the second side wall portions and the normal direction of the substrate is 1.0 degree or more;
Forming a seed layer on the first surface, the second surface and the through hole of the substrate using at least one of physical vapor deposition and sputtering;
By forming a plating layer on the seed layer, a first wiring layer located on the first surface and having conductivity, and a second wiring layer located on the second surface and having conductivity. Forming a through electrode located in the through hole, and
In the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the first wiring layer are formed so that the thicknesses of the seed layer of the first wiring layer and the seed layer of the second wiring layer are 1.0 μm or more. A method of manufacturing a through electrode substrate, wherein a seed layer of two wiring layers is formed and a seed layer of the through electrode is formed on a side wall of the through hole.   The method of manufacturing a through electrode substrate according to claim 7, wherein the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer are each formed by sputtering.   9. The through electrode substrate according to claim 7, wherein in the step of forming the seed layer, the seed layer of the first wiring layer and the seed layer of the second wiring layer are formed in a thickness range of 3.0 μm or less. Manufacturing method.   10. The method of manufacturing a through electrode substrate according to claim 7, wherein an angle formed between a side wall of the through hole and a normal direction of the substrate is 12 degrees or less.   The method of manufacturing a through electrode substrate according to claim 7, wherein the thickness of the substrate is 300 μm or more and 400 μm or less. A substrate including a first surface and a second surface located opposite to the first surface and provided with a through hole;
A first wiring layer located on the first surface and having conductivity;
A second wiring layer located on the second surface and having conductivity;
A through electrode located in the through hole,
The side wall of the through hole is tapered from the first surface to the second surface,
The angle formed by the side wall of the through hole and the normal direction of the substrate is 1.0 degree or more,
The through electrode is a conformal via provided on a side wall of the through hole, and electrically connects the first wiring layer and the second wiring layer,
Each of the through electrode, the first wiring layer, and the second wiring layer includes a seed layer and a plating layer,
The through electrode substrate, wherein each of the seed layer of the first wiring layer and the seed layer of the second wiring layer has a thickness of 1.0 μm or more. A substrate including a first surface and a second surface located opposite to the first surface and provided with a through hole;
A first wiring layer located on the first surface and having conductivity;
A second wiring layer located on the second surface and having conductivity;
A through electrode located in the through hole,
The side wall of the through hole is tapered from the first surface to the second surface,
The angle formed between the side wall of the through hole and the normal direction of the substrate is 0.8 degrees or more,
The through electrode is a conformal via provided on a side wall of the through hole, and electrically connects the first wiring layer and the second wiring layer,
Each of the through electrode, the first wiring layer, and the second wiring layer includes a seed layer and a plating layer,
Each of the thicknesses of the seed layer of the first wiring layer and the seed layer of the second wiring layer is 1.5 μm or more.   The through electrode substrate according to claim 12 or 13, wherein the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer are each formed of a sputtered layer.   15. The through electrode substrate according to claim 12, wherein each of the seed layer of the first wiring layer and the seed layer of the second wiring layer has a thickness of 3.0 μm or less.   The through electrode substrate according to claim 12, wherein an angle formed between a side wall of the through hole and a normal direction of the substrate is 12 degrees or less.   The through electrode substrate according to claim 12, wherein the substrate has a thickness of 300 μm or more and 400 μm or less. A substrate including a first surface and a second surface located opposite to the first surface and provided with a through hole;
A first wiring layer located on the first surface and having conductivity;
A second wiring layer located on the second surface and having conductivity;
A through electrode located in the through hole,
A tapered first side wall portion in which the side wall of the through hole tapers from the first surface toward the inner side of the substrate, and a tapered shape in which the side wall of the through hole tapers from the second surface toward the inner side of the substrate. A second side wall portion of
An angle formed between each of the first sidewall portion and the second sidewall portion of the through hole and a normal direction of the substrate is 1.0 degree or more,
The through electrode is a conformal via provided on a side wall of the through hole, and electrically connects the first wiring layer and the second wiring layer,
Each of the through electrode, the first wiring layer, and the second wiring layer includes a seed layer and a plating layer,
The through electrode substrate, wherein each of the seed layer of the first wiring layer and the seed layer of the second wiring layer has a thickness of 1.0 μm or more.   The through electrode substrate according to claim 18, wherein the seed layer of the through electrode, the seed layer of the first wiring layer, and the seed layer of the second wiring layer are each formed of a sputtered layer.   20. The through electrode substrate according to claim 18, wherein each thickness of the seed layer of the first wiring layer and the seed layer of the second wiring layer is 3.0 μm or less.   21. The through electrode substrate according to claim 18, wherein an angle formed between a side wall of the through hole and a normal direction of the substrate is 12 degrees or less.   The through electrode substrate according to any one of claims 18 to 21, wherein a thickness of the substrate is not less than 300 µm and not more than 400 µm.