JP6833864B2 - パワー半導体装置およびパワー半導体装置を作製するための方法 - Google Patents
パワー半導体装置およびパワー半導体装置を作製するための方法 Download PDFInfo
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Description
したがって、本発明の目的は、当該技術分野で公知の欠点のうち少なくとも1つを少なくとも部分的に防止することである。
接合終端部を有する表面に関して、第1の側および第2の側のうち少なくとも一方は、面取りされた態様または角度付けられた態様にそれぞれ形作られる端縁領域を備え、面取りされた端縁は接合終端部を備えるようにされ得る。この成形により、電位が分散される距離が大きくなり、これにより表面電界が低減され、こうして改良された実施形態になり得る。
a)p/n接合の接合終端部を有する少なくとも1つの表面を有する半導体基板を設けるステップと、
b)無機−有機複合材料、パリレン、およびポリマー粒子を備えるフェノール樹脂からなる群から選択される材料で接合終端部を被覆するステップとを備える。
図1に、本発明の実施形態に従うパワー半導体装置10の概略図が示される。パワー半導体装置10は、第1の側14および第2の側16を有する円盤形状の基板12を備える。第1の側14および第2の側16は互いに対して反対に位置する。第1の側14はカソード18を備え、第2の側16はアノード20を備え、カソード18とアノード20との両者は金属コンタクト19,21から形成される。第1の側14と第2の側16との両者は端縁領域22,24を備え、端縁領域22,24は面取りされた態様に形作られ、面取りされた端縁領域22,24はp−n接合を備えるが、そのようには示されていない。面取りされた端縁領域22,24は、少なくとも部分的に不動態化被膜26によって被覆され、不動態化被膜26は、無機−有機複合材料、パリレン、およびポリマー粒子を備えるフェノール樹脂からなる群から選択される少なくとも1つの材料を備える。詳細には、それぞれの負の面取り部がそれぞれ被覆される。
参照としてのシリコーンゴム単独(曲線A)に関して、本発明に従うすべての用いられた材料は、シリコーンゴム単独よりもはるかに(等しく)より良好である。
10 パワー半導体装置、12 基板、14 第1の側、16 第2の側、18 カソード、19 金属コンタクト、20 アノード、21 金属コンタクト、22 端縁領域、24 端縁領域、26 不動態化被膜、28 封入材
Claims (8)
- パワー半導体装置であって、
第1の側(14)および第2の側(16)を有する基板(12)を備え、前記第1の側(14)および前記第2の側(16)は互いに対して反対に位置し、前記第1の側(14)はカソード(18)を備え、前記第2の側(16)はアノード(20)を備え、p/n接合の接合終端部は、前記基板の少なくとも一方の表面に設けられ、
前記接合終端部は不動態化被膜(26)によって被覆され、前記不動態化被膜(26)はパリレンからなる材料を備えることを特徴とする、パワー半導体装置。 - パワー半導体装置であって、
第1の側(14)および第2の側(16)を有する基板(12)を備え、前記第1の側(14)および前記第2の側(16)は互いに対して反対に位置し、前記第1の側(14)はカソード(18)を備え、前記第2の側(16)はアノード(20)を備え、p/n接合の接合終端部は、前記基板の少なくとも一方の表面に設けられ、
前記接合終端部は不動態化被膜(26)によって被覆され、前記不動態化被膜(26)はポリマー粒子を備えるフェノール樹脂からなる材料を備えることを特徴とする、パワー半導体装置。 - 前記パリレンはパリレンFであることを特徴とする、請求項1に記載のパワー半導体装置。
- 前記フェノール樹脂はゴム粒子を備えることを特徴とする、請求項2に記載のパワー半導体装置。
- 前記基板の前記少なくとも一方の表面は、前記第1の側(14)および前記第2の側(16)のうち少なくとも一方であることを特徴とする、請求項1または請求項2に記載のパワー半導体装置。
- 前記不動態化被膜(26)は封入材(28)の中に少なくとも部分的に埋込まれることを特徴とする、請求項1から5のいずれか1項に記載のパワー半導体装置。
- 前記封入材(28)はゴム材料を備えることを特徴とする、請求項6に記載のパワー半導体装置。
- 前記不動態化被膜(26)はさらなる被覆の上に位置することを特徴とする、請求項1から7のいずれか1項に記載のパワー半導体装置。
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Application Number | Priority Date | Filing Date | Title |
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EP15193266 | 2015-11-05 | ||
EP15193266.2 | 2015-11-05 | ||
PCT/EP2016/075266 WO2017076659A1 (en) | 2015-11-05 | 2016-10-20 | Power semiconductor device and method for producing a power semiconductor device |
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JP2019502271A JP2019502271A (ja) | 2019-01-24 |
JP6833864B2 true JP6833864B2 (ja) | 2021-02-24 |
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US (1) | US10546795B2 (ja) |
JP (1) | JP6833864B2 (ja) |
CN (1) | CN108475665B (ja) |
DE (1) | DE112016005077T5 (ja) |
GB (1) | GB2558147B (ja) |
WO (1) | WO2017076659A1 (ja) |
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US10607831B2 (en) | 2017-05-04 | 2020-03-31 | International Business Machines Corporation | Thiourea organic compound for gallium arsenide based optoelectronics surface passivation |
CN112582480B (zh) * | 2020-12-15 | 2024-01-26 | 扬州杰利半导体有限公司 | 一种低中压台面tvs产品的pn结钝化工艺 |
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US3628106A (en) | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with protective peripheral junction portion |
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2016
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- 2016-10-20 WO PCT/EP2016/075266 patent/WO2017076659A1/en active Application Filing
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- 2016-10-20 GB GB1807386.6A patent/GB2558147B/en active Active
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GB2558147B (en) | 2020-11-11 |
DE112016005077T5 (de) | 2018-08-30 |
CN108475665A (zh) | 2018-08-31 |
US20180254233A1 (en) | 2018-09-06 |
US10546795B2 (en) | 2020-01-28 |
JP2019502271A (ja) | 2019-01-24 |
GB2558147A (en) | 2018-07-04 |
WO2017076659A1 (en) | 2017-05-11 |
CN108475665B (zh) | 2022-05-27 |
GB201807386D0 (en) | 2018-06-20 |
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