JP6832656B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6832656B2 JP6832656B2 JP2016179378A JP2016179378A JP6832656B2 JP 6832656 B2 JP6832656 B2 JP 6832656B2 JP 2016179378 A JP2016179378 A JP 2016179378A JP 2016179378 A JP2016179378 A JP 2016179378A JP 6832656 B2 JP6832656 B2 JP 6832656B2
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Description
Claims (2)
- 基板に酸化物半導体層を有する第1のTFTとPoly−Si層を有する第2のTFTが形成された半導体装置の製造方法であって、
前記酸化物半導体層を形成した後、前記酸化物半導体層の上または上方に第1の層間絶縁膜を形成し、
前記第1の層間絶縁膜の上にa−Si層を形成してパターニングを行い、その後レーザ照射をすることによって、Poly−Si層に変換することにより前記第2のTFTを形成し、
前記第2のTFTを第2の層間絶縁膜で覆い、前記第2のTFTと接続する第2のスルーホールを前記第2の層間絶縁膜を貫通して形成し、
前記第1のTFTと接続する第1のスルーホールを前記第2の層間絶縁膜と前記第1の層間絶縁膜を貫通して形成し、
前記第1のスルーホールと前記第2のスルーホールを同一プロセスで形成することを特徴とする半導体装置の製造方法。 - 前記a−Si層をパターニング後、半導体レーザ照射を行う前に前記a−Si層をアニールすることを特徴とする請求項1に記載の半導体装置の製造方法。
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