JP6827442B2 - 貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ - Google Patents

貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ Download PDF

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Publication number
JP6827442B2
JP6827442B2 JP2018114001A JP2018114001A JP6827442B2 JP 6827442 B2 JP6827442 B2 JP 6827442B2 JP 2018114001 A JP2018114001 A JP 2018114001A JP 2018114001 A JP2018114001 A JP 2018114001A JP 6827442 B2 JP6827442 B2 JP 6827442B2
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Prior art keywords
wafer
silicon layer
layer
insulating film
soi wafer
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JP2018114001A
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English (en)
Japanese (ja)
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JP2019216222A (ja
Inventor
俊和 今井
俊和 今井
吉田 和彦
和彦 吉田
美保 二井谷
美保 二井谷
大士 若林
大士 若林
石川 修
修 石川
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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Priority to JP2018114001A priority Critical patent/JP6827442B2/ja
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to US16/973,575 priority patent/US11495488B2/en
Priority to KR1020207035831A priority patent/KR20210020024A/ko
Priority to EP19819168.6A priority patent/EP3809448B1/fr
Priority to CN201980039406.1A priority patent/CN112262455A/zh
Priority to PCT/JP2019/019017 priority patent/WO2019239763A1/fr
Priority to SG11202011945RA priority patent/SG11202011945RA/en
Priority to TW108117570A priority patent/TWI804626B/zh
Publication of JP2019216222A publication Critical patent/JP2019216222A/ja
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Publication of JP6827442B2 publication Critical patent/JP6827442B2/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02595Microstructure polycrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
JP2018114001A 2018-06-14 2018-06-14 貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ Active JP6827442B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2018114001A JP6827442B2 (ja) 2018-06-14 2018-06-14 貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ
KR1020207035831A KR20210020024A (ko) 2018-06-14 2019-05-14 첩합soi웨이퍼의 제조방법 및 첩합soi웨이퍼
EP19819168.6A EP3809448B1 (fr) 2018-06-14 2019-05-14 Tranche soi liée et son procédé de fabrication
CN201980039406.1A CN112262455A (zh) 2018-06-14 2019-05-14 贴合soi晶圆的制造方法及贴合soi晶圆
US16/973,575 US11495488B2 (en) 2018-06-14 2019-05-14 Method for manufacturing bonded SOI wafer and bonded SOI wafer
PCT/JP2019/019017 WO2019239763A1 (fr) 2018-06-14 2019-05-14 Tranche soi liée et son procédé de fabrication
SG11202011945RA SG11202011945RA (en) 2018-06-14 2019-05-14 Method for manufacturing bonded soi wafer and bonded soi wafer
TW108117570A TWI804626B (zh) 2018-06-14 2019-05-21 貼合式soi晶圓的製造方法及貼合式soi晶圓

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018114001A JP6827442B2 (ja) 2018-06-14 2018-06-14 貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ

Publications (2)

Publication Number Publication Date
JP2019216222A JP2019216222A (ja) 2019-12-19
JP6827442B2 true JP6827442B2 (ja) 2021-02-10

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JP2018114001A Active JP6827442B2 (ja) 2018-06-14 2018-06-14 貼り合わせsoiウェーハの製造方法及び貼り合わせsoiウェーハ

Country Status (8)

Country Link
US (1) US11495488B2 (fr)
EP (1) EP3809448B1 (fr)
JP (1) JP6827442B2 (fr)
KR (1) KR20210020024A (fr)
CN (1) CN112262455A (fr)
SG (1) SG11202011945RA (fr)
TW (1) TWI804626B (fr)
WO (1) WO2019239763A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021190660A (ja) * 2020-06-04 2021-12-13 株式会社Sumco 貼り合わせウェーハ用の支持基板

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0246756A (ja) * 1988-08-08 1990-02-16 Mitsubishi Electric Corp 半導体容量素子の製造方法
US5229305A (en) * 1992-02-03 1993-07-20 Motorola, Inc. Method for making intrinsic gettering sites in bonded substrates
JPH06232390A (ja) * 1993-01-29 1994-08-19 Nippon Steel Corp 半導体装置のポリサイド配線の製造方法
JPH08186167A (ja) * 1994-12-27 1996-07-16 Mitsubishi Materials Shilicon Corp 張り合わせ誘電体分離ウェーハの製造方法
US8299537B2 (en) 2009-02-11 2012-10-30 International Business Machines Corporation Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region
US8786051B2 (en) * 2012-02-21 2014-07-22 International Business Machines Corporation Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance
FR3019373A1 (fr) 2014-03-31 2015-10-02 St Microelectronics Sa Procede de fabrication d'une plaque de semi-conducteur adaptee pour la fabrication d'un substrat soi et plaque de substrat ainsi obtenue
JP6100200B2 (ja) 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP6118757B2 (ja) 2014-04-24 2017-04-19 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP6156252B2 (ja) * 2014-05-16 2017-07-05 株式会社豊田自動織機 半導体基板の製造方法および半導体基板
JP2015228432A (ja) * 2014-06-02 2015-12-17 信越半導体株式会社 Soiウェーハの製造方法及び貼り合わせsoiウェーハ
EP3221884B1 (fr) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. Plaquettes de semi-conducteur sur isolant à haute résistivité comprenant couches de piégeage de charges et son procédé de fabrication.
JP2016143820A (ja) 2015-02-04 2016-08-08 信越半導体株式会社 貼り合わせ半導体ウェーハ及びその製造方法
WO2016140850A1 (fr) 2015-03-03 2016-09-09 Sunedison Semiconductor Limited Procédé pour déposer des films de silicium polycristallin de piégeage de charge sur des substrats de silicium avec une contrainte de film pouvant être maîtrisée
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP6443394B2 (ja) * 2016-06-06 2018-12-26 信越半導体株式会社 貼り合わせsoiウェーハの製造方法

Also Published As

Publication number Publication date
JP2019216222A (ja) 2019-12-19
TWI804626B (zh) 2023-06-11
WO2019239763A1 (fr) 2019-12-19
US11495488B2 (en) 2022-11-08
EP3809448A4 (fr) 2022-03-02
TW202001988A (zh) 2020-01-01
CN112262455A (zh) 2021-01-22
EP3809448B1 (fr) 2023-03-01
SG11202011945RA (en) 2021-01-28
KR20210020024A (ko) 2021-02-23
US20210249301A1 (en) 2021-08-12
EP3809448A1 (fr) 2021-04-21

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