SG11202011945RA - Method for manufacturing bonded soi wafer and bonded soi wafer - Google Patents

Method for manufacturing bonded soi wafer and bonded soi wafer

Info

Publication number
SG11202011945RA
SG11202011945RA SG11202011945RA SG11202011945RA SG11202011945RA SG 11202011945R A SG11202011945R A SG 11202011945RA SG 11202011945R A SG11202011945R A SG 11202011945RA SG 11202011945R A SG11202011945R A SG 11202011945RA SG 11202011945R A SG11202011945R A SG 11202011945RA
Authority
SG
Singapore
Prior art keywords
soi wafer
bonded soi
manufacturing
bonded
wafer
Prior art date
Application number
SG11202011945RA
Inventor
Toshikazu Imai
Kazuhiko Yoshida
Miho NIITANI
Taishi Wakabayashi
Osamu Ishikawa
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of SG11202011945RA publication Critical patent/SG11202011945RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
SG11202011945RA 2018-06-14 2019-05-14 Method for manufacturing bonded soi wafer and bonded soi wafer SG11202011945RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018114001A JP6827442B2 (en) 2018-06-14 2018-06-14 Manufacturing method of bonded SOI wafer and bonded SOI wafer
PCT/JP2019/019017 WO2019239763A1 (en) 2018-06-14 2019-05-14 Bonded soi wafer and method for manufacturing bonded soi wafer

Publications (1)

Publication Number Publication Date
SG11202011945RA true SG11202011945RA (en) 2021-01-28

Family

ID=68843208

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202011945RA SG11202011945RA (en) 2018-06-14 2019-05-14 Method for manufacturing bonded soi wafer and bonded soi wafer

Country Status (8)

Country Link
US (1) US11495488B2 (en)
EP (1) EP3809448B1 (en)
JP (1) JP6827442B2 (en)
KR (1) KR20210020024A (en)
CN (1) CN112262455A (en)
SG (1) SG11202011945RA (en)
TW (1) TWI804626B (en)
WO (1) WO2019239763A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021190660A (en) * 2020-06-04 2021-12-13 株式会社Sumco Support substrate for bonded wafers

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0246756A (en) * 1988-08-08 1990-02-16 Mitsubishi Electric Corp Manufacture of semiconductor capacitor
US5229305A (en) * 1992-02-03 1993-07-20 Motorola, Inc. Method for making intrinsic gettering sites in bonded substrates
JPH06232390A (en) * 1993-01-29 1994-08-19 Nippon Steel Corp Manufacture of polycide wiring of semiconductor device
JPH08186167A (en) * 1994-12-27 1996-07-16 Mitsubishi Materials Shilicon Corp Manufacture of laminated dielectric isolation wafer
US8299537B2 (en) 2009-02-11 2012-10-30 International Business Machines Corporation Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region
US8786051B2 (en) * 2012-02-21 2014-07-22 International Business Machines Corporation Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance
FR3019373A1 (en) 2014-03-31 2015-10-02 St Microelectronics Sa METHOD FOR MANUFACTURING SEMICONDUCTOR PLATE ADAPTED FOR MANUFACTURING SOI SUBSTRATE AND SUBSTRATE PLATE THUS OBTAINED
JP6100200B2 (en) 2014-04-24 2017-03-22 信越半導体株式会社 Manufacturing method of bonded SOI wafer
JP6118757B2 (en) 2014-04-24 2017-04-19 信越半導体株式会社 Manufacturing method of bonded SOI wafer
JP6156252B2 (en) * 2014-05-16 2017-07-05 株式会社豊田自動織機 Semiconductor substrate manufacturing method and semiconductor substrate
JP2015228432A (en) * 2014-06-02 2015-12-17 信越半導体株式会社 Soi wafer manufacturing method and bonded soi wafer
EP3221884B1 (en) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
JP2016143820A (en) 2015-02-04 2016-08-08 信越半導体株式会社 Semiconductor bonding wafer and method of manufacturing the same
WO2016140850A1 (en) 2015-03-03 2016-09-09 Sunedison Semiconductor Limited Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
JP6353814B2 (en) * 2015-06-09 2018-07-04 信越半導体株式会社 Manufacturing method of bonded SOI wafer
JP6443394B2 (en) * 2016-06-06 2018-12-26 信越半導体株式会社 Manufacturing method of bonded SOI wafer

Also Published As

Publication number Publication date
JP2019216222A (en) 2019-12-19
TWI804626B (en) 2023-06-11
WO2019239763A1 (en) 2019-12-19
US11495488B2 (en) 2022-11-08
EP3809448A4 (en) 2022-03-02
TW202001988A (en) 2020-01-01
CN112262455A (en) 2021-01-22
JP6827442B2 (en) 2021-02-10
EP3809448B1 (en) 2023-03-01
KR20210020024A (en) 2021-02-23
US20210249301A1 (en) 2021-08-12
EP3809448A1 (en) 2021-04-21

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