JP6807911B2 - 磁気トンネル接合装置の製造技術と対応装置 - Google Patents
磁気トンネル接合装置の製造技術と対応装置 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N50/00—Galvanomagnetic devices
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Description
264a 周辺領域の上面、266 下強磁性電極、266’ 下強磁性層、268 上強磁性電極、268’ 上強磁性層、270 トンネルバリア層、270’ トンネルバリア層、272 キャッピング層、272’ キャッピング層、274 上部ピン強磁性層、274’ 上強磁性電極層、276 底部ピン強磁性層、276’ 下強磁性電極層、278 金属層、278’ 金属層、500 半導体構造の製造方法、502〜520 方法500の工程、600 断面図、700 断面図、702 第一マスク、704 第一エッチング、706 開口、800 断面図、900 断面図、902 マスク、1000 断面図、1002 第二エッチング、1100 断面図、1200 断面図、1300 断面図、1302 第三エッチング、1400 断面図、1500 断面図、1600 断面図。
Claims (10)
- 磁気抵抗ランダムアクセスメモリ(MRAM)セルを含む集積回路であって、
半導体基板と、
前記半導体基板上に設けられたビアと、
前記ビア上に設けられた金属線と、
前記金属線の上面を部分的に被覆するエッチング停止層と、
前記エッチング停止層に積層された周辺部分と、前記エッチング停止層の開口を通して前記金属線の上面に結合するまで下方に延伸しかつ前記周辺部分と接続している中央部分とを含み、当該中央部分が前記ビアの幅に等しい幅を有した、前記エッチング停止層上の底部電極と、
前記底部電極の前記中央部分上の磁気トンネル接合と、
前記磁気トンネル接合上の上部電極と、
前記底部電極の前記周辺部分の上面から前記上部電極の上面までの高さが単調に増加または実質的に平坦である外側壁を有しており、前記磁気トンネル接合の側壁に直接結合され、前記磁気トンネル接合の側壁と前記上部電極の側壁に沿って、前記底部電極の前記周辺部分の上面に延伸して直接結合した側壁スペーサと、
を備えたことを特徴とする集積回路。 - 半導体基板上の相互接続構造に設けられた磁気抵抗ランダムアクセスメモリ(MRAM)セルを含む集積回路であって、
ビア上に配置された金属線の上面を部分的に被覆するエッチング停止層と、
前記エッチング停止層に積層された周辺部分と、前記エッチング停止層の開口を通して前記金属線の上面に結合するまで延伸しかつ前記周辺部分と接続している中央部分とを含み、当該中央部分が前記ビアの幅に等しい幅を有した、底部電極と、
前記底部電極の中央部分上の磁気トンネル接合と、
前記磁気トンネル接合上の上部電極と、
前記底部電極の周辺部分の上面から前記上部電極の上面までの高さが単調に増加または実質的に平坦である外側壁を有しており、底面と前記底部電極の上面とが直接結合され、前記底部電極の周辺部分の上方に設けられた側壁スペーサと、
を備えたことを特徴とする集積回路。 - 前記底部電極の中央部分の上面が周辺部分の上面に対して窪むように、前記底部電極の階段部分が中央部分と周辺部分とを互いに結合していることを特徴とする請求項1または請求項2記載の集積回路。
- 前記底部電極の階段部分は、前記エッチング停止層の内側壁に沿って下方に延伸して、前記底部電極の中央部分と結合していることを特徴とする請求項3記載の集積回路。
- 前記底部電極の中央部分は、最も内側の周囲長内が実質的に連続して平坦であることを特徴とする請求項1から請求項4のいずれか1項記載の集積回路。
- 前記金属線は、前記底部電極と結合するビアまたはコンタクトなしに、前記底部電極と電気的に結合されていることを特徴とする請求項1から請求項5のいずれか1項記載の集積回路。
- 半導体基板上で、ビア上に設けられた金属線を含む相互接続構造に設けられた磁気抵抗ランダムアクセスメモリ(MRAM)セルを含む集積回路であって、
前記金属線の上面に設けられた誘電体保護層と、
前記誘電体保護層に積層された周辺部分と、前記誘電体保護層の開口を通して前記金属線の上面に結合するまで下方に延伸しかつ前記周辺部分と接続している中央部分とを含み、当該中央部分が前記ビアの幅に等しい幅を有した底部電極と、
前記底部電極の中央部分上の磁気トンネル接合と、
前記磁気トンネル接合上の上部電極と、
前記磁気トンネル接合の側壁および前記上部電極の側壁に直接結合され、前記底部電極の周辺部分の上面から前記上部電極の上面までの高さが単調に増加または実質的に平坦である外側壁を有しており、前記底部電極の周辺部分の上方に設けられて直接結合した側壁スペーサと、
を備えたことを特徴とする集積回路。 - 前記底部電極の中央部分の上面が周辺部分の上面に対して窪むように、前記底部電極の階段部分が中央部分と周辺部分とを互いに結合していることを特徴とする請求項7記載の集積回路。
- 前記底部電極の階段部分は、前記誘電体保護層の内側壁に沿って下方に延伸して、前記底部電極の中央部分と結合していることを特徴とする請求項8記載の集積回路。
- 前記底部電極の中央部分、階段部分および周辺部分は、連続したシームレス本体であることを特徴とする請求項1から請求項9のいずれか1項記載の集積回路。
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JP2018219116A Active JP6807911B2 (ja) | 2015-07-17 | 2018-11-22 | 磁気トンネル接合装置の製造技術と対応装置 |
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