JP6732025B2 - 炭化ケイ素超接合パワーデバイス用のエッジ終端設計 - Google Patents
炭化ケイ素超接合パワーデバイス用のエッジ終端設計 Download PDFInfo
- Publication number
- JP6732025B2 JP6732025B2 JP2018530717A JP2018530717A JP6732025B2 JP 6732025 B2 JP6732025 B2 JP 6732025B2 JP 2018530717 A JP2018530717 A JP 2018530717A JP 2018530717 A JP2018530717 A JP 2018530717A JP 6732025 B2 JP6732025 B2 JP 6732025B2
- Authority
- JP
- Japan
- Prior art keywords
- sic
- semiconductor layer
- regions
- sic semiconductor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 133
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 126
- 238000013461 design Methods 0.000 title description 26
- 239000004065 semiconductor Substances 0.000 claims description 95
- 239000007943 implant Substances 0.000 claims description 84
- 238000002513 implantation Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 230000007423 decrease Effects 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 170
- 239000002019 doping agent Substances 0.000 description 30
- 230000005684 electric field Effects 0.000 description 18
- 230000015556 catabolic process Effects 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 16
- 230000002441 reversible effect Effects 0.000 description 10
- 230000000903 blocking effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000003607 modifier Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66022—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6603—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Description
式1
式2
6A 終端領域、終端部
6B 終端領域、終端部
6C 終端領域、終端部
7 界面
8 活性領域
9 外側端部
10 SiC−SJデバイス、SiC−SJパワーデバイス、SiC−SJショットキーデバイス、SiC−SJ構造
12 上部コンタクト
14 誘電層
18 底部コンタクト
20 SiC基板層
24 エピタキシャルSiC層、SiCエピタキシャル層、初期層、エピ層
24A 終端領域
24B 活性領域
26 エピタキシャルSiC層、SiCエピタキシャル層、エピ層
26A 終端領域
26B 活性領域
28 エピタキシャルSiC層、SiCエピタキシャル層、エピ層、
28A 終端領域
28B 活性領域
30 厚さ
32 厚さ
34 厚さ
36 フローティング領域、注入領域
38 フローティング領域、注入領域
40 電荷バランス領域、フローティング領域、注入領域
42 厚さ
44 幅
46 間隔
50 等電位線
52 矢印
54 破線
60 SiC−SJデバイス
62 連続的なピラー、連続した垂直ピラー
70 グラフ
72 曲線
74 曲線
80 SiC−SJデバイス
90 降伏電圧感度輪郭プロット
92 曲線
94 曲線
96 曲線
98 曲線
100 曲線
102 曲線
110 SiC−SJデバイス
120 降伏電圧感度輪郭プロット
122 キー
130 グラフ
132 垂直線、注入領域
134 垂直線
140 ストライプセル
150 正方形のセル
160 湾曲コーナ
Claims (21)
- 第1の導電型の複数のSiC半導体層を備え、前記複数のSiC半導体層の第1および第2のSiC半導体層は、それらの間に界面(7)を形成して活性領域(8、24B、26B、28B)に隣接して配置された終端領域(6、24A、26A、28A)を備え、前記第1および前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)は、第2の導電型の複数の注入領域(36、38、40、132)を備え、前記第1のSiC半導体層の前記終端領域(6、24A、26A、28A)の有効ドーピングプロファイルは、前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の有効ドーピングプロファイルとは異なり、
各前記複数の注入領域(36、38、40、132)が、それぞれの幅(44)を有し、前記複数の注入領域(36、38、40、132)の前記それぞれの幅(44)が、約0.8μm〜約5μmである、
炭化ケイ素(SiC)超接合(SJ)デバイス(10、60、80、110)。 - 前記複数の注入領域(36、38、40、132)の少なくとも一部が、フローティング領域(36、38、40)である、請求項1に記載のSiC−SJデバイス(10、60、80、110)。
- 前記複数の注入領域(36、38、40、132)の少なくとも1つの注入領域(36、38、40、132)が、前記複数のSiC半導体層の厚さ全体を通って延びる、請求項1に記載のSiC−SJデバイス(10、60、80、110)。
- 前記第1または前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の各前記複数の注入領域(36、38、40、132)が、それぞれの幅(44)を有し、前記複数の注入領域(36、38、40、132)の前記それぞれの幅(44)が、前記第1または前記第2のSiC半導体層内の前記終端領域(6、24A、26A、28A)の前記幅(44)に沿って前記活性領域(8、24B、26B、28B)と前記終端領域(6、24A、26A、28A)との間の前記界面(7)からの距離が増加するにつれて減少する、請求項1に記載のSiC−SJデバイス(10、60、80、110)。
- 前記第1または前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の前記複数の注入領域(36、38、40、132)の間の間隔(46)が、前記第1または前記第2のSiC半導体層内の前記終端領域(6、24A、26A、28A)の前記幅(44)に沿って前記活性領域(8、24B、26B、28B)と前記終端領域(6、24A、26A、28A)との間の前記界面(7)からの距離が増加しても実質的に一定のままである、請求項4に記載のSiC−SJデバイス(10、60、80、110)。
- 前記第1または前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の前記複数の注入領域(36、38、40、132)の間の間隔(46)が、前記第1または前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の前記幅(44)に沿って前記活性領域(8、24B、26B、28B)と前記終端領域(6、24A、26A、28A)との間の前記界面(7)からの距離が増加するにつれて増加または減少する、請求項1に記載のSiC−SJデバイス(10、60、80、110)。
- 各前記複数の注入領域(36、38、40、132)が、それぞれの幅(44)を有し、前記複数の注入領域(36、38、40、132)の前記それぞれの幅(44)が、前記第1または前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の前記幅(44)に沿って前記活性領域(8、24B、26B、28B)と前記終端領域(6、24A、26A、28A)との間の前記界面(7)からの距離が増加しても実質的に一定のままである、請求項6に記載のSiC−SJデバイス(10、60、80、110)。
- 前記第1のSiC半導体層の前記終端領域(6、24A、26A、28A)の前記複数の注入領域(36、38、40、132)の厚さ(42)、幅(44)、間隔(46)およびドーピング濃度の1つまたは複数が、前記第2のSiC半導体層の前記終端領域(6、24A、26A、28A)の前記複数の注入領域(36、38、40、132)のそれぞれの厚さ(42)、幅(44)、間隔(46)、およびドーピング濃度とは異なる、請求項1に記載のSiC−SJデバイス(10、60、80、110)。
- 第1の導電型の第1のSiC半導体層であって、前記第1のSiC半導体層は、前記第1のSiC半導体層の活性領域(8、24B、26B、28B)および終端領域(6、24A、26A、28A)を形成する第2の導電型の第1の複数の注入領域(36、38、40、132)を備え、前記第1のSiC半導体層の前記終端領域(6、24A、26A、28A)は、第1の有効ドーピングプロファイルを有する第1のSiC半導体層と、
前記第1のSiC半導体層の下に配置され、前記第1のSiC半導体層より基板層(20)に近い前記第1の導電型の少なくとも1つの第2のSiC半導体層であって、前記少なくとも1つの第2のSiC半導体層は、前記少なくとも1つの第2のSiC半導体層の第2の活性領域(8、24B、26B、28B)および第2の終端領域(6、24A、26A、28A)を形成する前記第2の導電型の第2の複数の注入領域(36、38、40、132)を含み、前記少なくとも1つの第2のSiC半導体層の前記第2の終端領域(6、24A、26A、28A)は、前記第1の有効ドーピングプロファイルとは異なる第2の有効ドーピングプロファイルを有する第2のSiC半導体層とを備え、
前記第1の有効ドーピングプロファイルが、以下の式によって定義され、
炭化ケイ素(SiC)超接合(SJ)デバイス(10、60、80、110)。 - 前記活性領域(8、24B、26B、28B)の前記複数の注入領域(36、38、40、132)が、ストライプセル(140)を形成するように整列されるか、または正方形のセル(150)を形成するように互い違いに配置される、請求項9に記載のSiC−SJデバイス(10、60、80、110)。
- 3×1013cm−2>Nmax>(6×1012cm−2−Qinterface)であって、
Qinterfaceが、界面電荷である、請求項9に記載のSiC−SJデバイス(10、60、80、110)。 - Nminが、Nmaxの約10%〜Nmaxの約50%であり、Nminが、前記第1のSiC半導体層の第1の導電型のシートドーピング濃度以上である、請求項9に記載のSiC−SJデバイス(10、60、80、110)。
- 前記第2の有効ドーピングプロファイルが、以下の式によって定義され、
- Nmaxが、前記少なくとも1つの第2のSiC半導体層の前記活性領域(8、24B、26B、28B)の最大有効シートドーピングと実質的に等しく、前記少なくとも1つの第2のSiC半導体層の前記活性領域(8、24B、26B、28B)と前記終端領域(6、24A、26A、28A)との間に実質的にシームレスな接続をもたらす、請求項13に記載のSiC−SJデバイス(10、60、80、110)。
- 6×1012cm−2<Nmax<3×1013cm−2である、請求項13に記載の
SiC−SJデバイス(10、60、80、110)。 - Nminが、Nmaxの約10%〜Nmaxの約50%であり、Nminが、前記少なくとも1つの第2のSiC半導体層の第1の導電型のシートドーピング密度以上である、請求項13に記載のSiC−SJデバイス(10、60、80、110)。
- 炭化ケイ素(SiC)超接合(SJ)デバイス(10、60、80、110)を製造する方法であって、
第1の導電型を有する下側SiC半導体層をSiC基板層(20)の上部に形成すること、
第2の導電型を有する第1の複数の注入領域(40)を前記下側SiC半導体層の一部に形成することによって活性領域(8、24B、26B、28B)を前記下側SiC半導体層に作製すること、および
第1の有効ドーピングプロファイルに従って前記第2の導電型を有する第2の複数の注入領域(36、38、132)を前記活性領域(8、24B、26B、28B)に隣接する前記下側SiC半導体層の別の部分に形成することによって終端領域(6、24A、26A、28A)を前記下側SiC半導体層に作製すること、
を含む前記SiC−SJデバイス(10、60、80、110)の前記下側SiC半導体層を作製することと、
前記第1の導電型を有する上部SiC半導体層を前記下側SiC半導体層の上に形成すること、
前記第2の導電型を有する第3の複数の注入領域(40)を前記上部SiC半導体層の一部に形成することによって活性領域(8、24B、26B、28B)を前記上部SiC半導体層に作製すること、および
第2の有効ドーピングプロファイルに従って前記第2の導電型を有する第4の複数の注入領域(36、38、132)を前記活性領域(8、24B、26B、28B)に隣接する前記上部SiC半導体層の別の部分に形成することによって終端領域(6、24A、26A、28A)を前記上部SiC半導体層に作製すること、
を含む前記SiC−SJデバイス(10、60、80、110)の前記上部SiC半導体層を作製することとを含み、前記第1の有効ドーピングプロファイルは、前記第2の有効ドーピングプロファイルとは異なり、前記第1、第2、第3および第4の複数の注入領域(36、38、40、132)の1以上が、約400keV未満の注入エネルギを使用して注入される、方法。 - 前記第1の複数の注入領域(40)および前記第2の複数の注入領域(36、38、132)が、同じ注入量を使用して注入され、前記第3の複数の注入領域(40)および前記第4の複数の注入領域(36、38、132)が、同じ注入量を使用して注入される、請求項17に記載の方法。
- 前記第1、第2、第3、または第4の複数の注入領域(36、38、40、132)の少なくとも1つが、約400keVより大きい注入エネルギを使用して注入される、請求項17に記載の方法。
- 前記第1の複数の注入領域(40)および前記第2の複数の注入領域(36、38、132)を形成することが、前記第1の複数の注入領域(40)および前記第2の複数の注入領域(36、38、132)を約1μm以下の深さまで注入することを含む、請求項17に記載の方法。
- 前記第1の複数の注入領域(40)および前記第2の複数の注入領域(36、38、132)が、単一の注入ステップを使用して形成され、前記第3の複数の注入領域(40)および前記第4の複数の注入領域(36、38、132)が、別の単一の注入ステップを使用して形成される、請求項17に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2015/065881 WO2017105414A1 (en) | 2015-12-15 | 2015-12-15 | Edge termination designs for silicon carbide super-junction power devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019503071A JP2019503071A (ja) | 2019-01-31 |
JP6732025B2 true JP6732025B2 (ja) | 2020-07-29 |
Family
ID=55071207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018530717A Active JP6732025B2 (ja) | 2015-12-15 | 2015-12-15 | 炭化ケイ素超接合パワーデバイス用のエッジ終端設計 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10541338B2 (ja) |
EP (2) | EP4379808A2 (ja) |
JP (1) | JP6732025B2 (ja) |
CN (1) | CN108369963B (ja) |
WO (1) | WO2017105414A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9704949B1 (en) * | 2016-06-30 | 2017-07-11 | General Electric Company | Active area designs for charge-balanced diodes |
US11233157B2 (en) * | 2018-09-28 | 2022-01-25 | General Electric Company | Systems and methods for unipolar charge balanced semiconductor power devices |
US10957759B2 (en) | 2018-12-21 | 2021-03-23 | General Electric Company | Systems and methods for termination in silicon carbide charge balance power devices |
US11031472B2 (en) * | 2018-12-28 | 2021-06-08 | General Electric Company | Systems and methods for integrated diode field-effect transistor semiconductor devices |
US11373857B2 (en) * | 2019-05-14 | 2022-06-28 | Infineon Technologies Ag | Semiconductor surface smoothing and semiconductor arrangement |
JP7107284B2 (ja) * | 2019-07-08 | 2022-07-27 | 株式会社デンソー | 半導体装置とその製造方法 |
CN112993008A (zh) * | 2019-12-13 | 2021-06-18 | 南通尚阳通集成电路有限公司 | 电荷平衡器件及其制造方法 |
CN113555447B (zh) * | 2021-06-09 | 2024-02-09 | 浙江芯科半导体有限公司 | 一种基于金刚石终端结构的4H-SiC肖特基二极管及制作方法 |
CN114497182A (zh) * | 2021-12-16 | 2022-05-13 | 陕西半导体先导技术中心有限公司 | 一种基于体内多区终端结构的功率器件及制备方法 |
CN114497179A (zh) * | 2021-12-16 | 2022-05-13 | 苏州锴威特半导体股份有限公司 | 一种功率器件的体内多段终端结构及制备方法 |
CN114864704B (zh) * | 2022-07-11 | 2022-09-27 | 成都功成半导体有限公司 | 具有终端保护装置的碳化硅jbs及其制备方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03173180A (ja) * | 1989-12-01 | 1991-07-26 | Hitachi Ltd | 半導体素子 |
US6037632A (en) | 1995-11-06 | 2000-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP3804375B2 (ja) * | 1999-12-09 | 2006-08-02 | 株式会社日立製作所 | 半導体装置とそれを用いたパワースイッチング駆動システム |
US6642558B1 (en) * | 2000-03-20 | 2003-11-04 | Koninklijke Philips Electronics N.V. | Method and apparatus of terminating a high voltage solid state device |
JP3908572B2 (ja) | 2002-03-18 | 2007-04-25 | 株式会社東芝 | 半導体素子 |
JP2006073740A (ja) * | 2004-09-01 | 2006-03-16 | Toshiba Corp | 半導体装置及びその製造方法 |
US7737469B2 (en) | 2006-05-16 | 2010-06-15 | Kabushiki Kaisha Toshiba | Semiconductor device having superjunction structure formed of p-type and n-type pillar regions |
US7595241B2 (en) | 2006-08-23 | 2009-09-29 | General Electric Company | Method for fabricating silicon carbide vertical MOSFET devices |
US7948033B2 (en) | 2007-02-06 | 2011-05-24 | Semiconductor Components Industries, Llc | Semiconductor device having trench edge termination structure |
US9640609B2 (en) * | 2008-02-26 | 2017-05-02 | Cree, Inc. | Double guard ring edge termination for silicon carbide devices |
US7842590B2 (en) * | 2008-04-28 | 2010-11-30 | Infineon Technologies Austria Ag | Method for manufacturing a semiconductor substrate including laser annealing |
JP5636203B2 (ja) | 2009-03-26 | 2014-12-03 | 株式会社Sumco | 半導体基板、半導体装置及び半導体基板の製造方法 |
US8476698B2 (en) | 2010-02-19 | 2013-07-02 | Alpha And Omega Semiconductor Incorporated | Corner layout for superjunction device |
CN102214689B (zh) | 2010-04-06 | 2012-11-07 | 上海华虹Nec电子有限公司 | 超级结器件的终端保护结构及其制造方法 |
CN102738232B (zh) | 2011-04-08 | 2014-10-22 | 无锡维赛半导体有限公司 | 超结功率晶体管结构及其制作方法 |
US20130087852A1 (en) | 2011-10-06 | 2013-04-11 | Suku Kim | Edge termination structure for power semiconductor devices |
US8546875B1 (en) | 2012-03-14 | 2013-10-01 | Infineon Technologies Austria Ag | Vertical transistor having edge termination structure |
CN104303314B (zh) * | 2012-05-17 | 2017-05-24 | 通用电气公司 | 具有结终端扩展的半导体器件 |
CN105190852B (zh) * | 2013-03-15 | 2018-09-11 | 美国联合碳化硅公司 | 改进的vjfet器件 |
US9209292B2 (en) * | 2013-07-18 | 2015-12-08 | Infineon Technologies Austria Ag | Charge compensation semiconductor devices |
US9064738B2 (en) * | 2013-07-19 | 2015-06-23 | Cree, Inc. | Methods of forming junction termination extension edge terminations for high power semiconductor devices and related semiconductor devices |
US9735237B2 (en) * | 2015-06-26 | 2017-08-15 | General Electric Company | Active area designs for silicon carbide super-junction power devices |
-
2015
- 2015-12-15 EP EP24171136.5A patent/EP4379808A2/en active Pending
- 2015-12-15 JP JP2018530717A patent/JP6732025B2/ja active Active
- 2015-12-15 CN CN201580085384.4A patent/CN108369963B/zh active Active
- 2015-12-15 US US16/060,549 patent/US10541338B2/en active Active
- 2015-12-15 EP EP15820755.5A patent/EP3391417A1/en not_active Ceased
- 2015-12-15 WO PCT/US2015/065881 patent/WO2017105414A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
WO2017105414A1 (en) | 2017-06-22 |
EP4379808A2 (en) | 2024-06-05 |
JP2019503071A (ja) | 2019-01-31 |
US20190006529A1 (en) | 2019-01-03 |
CN108369963A (zh) | 2018-08-03 |
US10541338B2 (en) | 2020-01-21 |
EP3391417A1 (en) | 2018-10-24 |
CN108369963B (zh) | 2022-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6732025B2 (ja) | 炭化ケイ素超接合パワーデバイス用のエッジ終端設計 | |
JP7206029B2 (ja) | 電荷平衡jbsダイオードのための活性領域設計 | |
JP5052025B2 (ja) | 電力用半導体素子 | |
JP6861171B2 (ja) | 炭化ケイ素超接合パワーデバイスの活性領域設計および対応する方法 | |
US10586846B2 (en) | System and method for edge termination of super-junction (SJ) devices | |
US20100200931A1 (en) | Mosfet devices and methods of making | |
JP3634848B2 (ja) | 電力用半導体素子 | |
US9425265B2 (en) | Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure | |
JP2006005275A (ja) | 電力用半導体素子 | |
JP2006179598A (ja) | 電力用半導体装置 | |
JP2008258443A (ja) | 電力用半導体素子及びその製造方法 | |
US20180358477A1 (en) | Trench type junction barrier schottky diode and manufacturing method thereof | |
JP5559232B2 (ja) | 電力用半導体素子 | |
US8704302B2 (en) | Power semiconductor devices and methods | |
JPWO2013161116A1 (ja) | 半導体装置及びその製造方法 | |
JP6750300B2 (ja) | 半導体装置および半導体装置の製造方法 | |
KR20130049919A (ko) | 실리콘카바이드 쇼트키 배리어 다이오드 소자 및 이의 제조 방법 | |
US11271076B2 (en) | Systems and methods for junction termination in semiconductor devices | |
US10672883B2 (en) | Mixed trench junction barrier Schottky diode and method fabricating same | |
CN109155335B (zh) | 半导体器件及其制造方法 | |
JP2015225934A (ja) | 半導体装置 | |
CN111373546B (zh) | 宽带隙半导体装置 | |
CN115911097A (zh) | 一种用于SiC功率器件的复合终端结构及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181207 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20190806 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191009 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191024 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200113 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200218 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200514 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200609 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200707 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6732025 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |