JP6685126B2 - 半導体製造装置および半導体装置の製造方法 - Google Patents

半導体製造装置および半導体装置の製造方法 Download PDF

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Publication number
JP6685126B2
JP6685126B2 JP2015251207A JP2015251207A JP6685126B2 JP 6685126 B2 JP6685126 B2 JP 6685126B2 JP 2015251207 A JP2015251207 A JP 2015251207A JP 2015251207 A JP2015251207 A JP 2015251207A JP 6685126 B2 JP6685126 B2 JP 6685126B2
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die
wafer
unit
illumination
manufacturing apparatus
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JP2015251207A
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Japanese (ja)
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JP2017117916A5 (enExample
JP2017117916A (ja
Inventor
英晴 小橋
英晴 小橋
光央 依田
光央 依田
僚 大森
僚 大森
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Fasford Technology Co Ltd
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Fasford Technology Co Ltd
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Priority to JP2015251207A priority Critical patent/JP6685126B2/ja
Priority to TW105135961A priority patent/TWI624887B/zh
Priority to KR1020160153608A priority patent/KR20170076545A/ko
Priority to CN201611028994.3A priority patent/CN106920762B/zh
Publication of JP2017117916A publication Critical patent/JP2017117916A/ja
Publication of JP2017117916A5 publication Critical patent/JP2017117916A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/10Beam splitting or combining systems
    • G02B27/14Beam splitting or combining systems operating by reflection only
    • G02B27/141Beam splitting or combining systems operating by reflection only using dichroic mirrors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68721Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
JP2015251207A 2015-12-24 2015-12-24 半導体製造装置および半導体装置の製造方法 Active JP6685126B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2015251207A JP6685126B2 (ja) 2015-12-24 2015-12-24 半導体製造装置および半導体装置の製造方法
TW105135961A TWI624887B (zh) 2015-12-24 2016-11-04 半導體製造裝置及半導體裝置的製造方法
KR1020160153608A KR20170076545A (ko) 2015-12-24 2016-11-17 반도체 제조 장치 및 반도체 장치의 제조 방법
CN201611028994.3A CN106920762B (zh) 2015-12-24 2016-11-18 半导体制造装置、半导体器件的制造方法及芯片贴装机

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015251207A JP6685126B2 (ja) 2015-12-24 2015-12-24 半導体製造装置および半導体装置の製造方法

Publications (3)

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JP2017117916A JP2017117916A (ja) 2017-06-29
JP2017117916A5 JP2017117916A5 (enExample) 2019-01-24
JP6685126B2 true JP6685126B2 (ja) 2020-04-22

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JP (1) JP6685126B2 (enExample)
KR (1) KR20170076545A (enExample)
CN (1) CN106920762B (enExample)
TW (1) TWI624887B (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7082862B2 (ja) * 2017-07-27 2022-06-09 ファスフォードテクノロジ株式会社 ダイボンディング装置、半導体装置の製造方法および半導体製造システム
JP7029900B2 (ja) * 2017-08-03 2022-03-04 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
JP7010633B2 (ja) * 2017-09-19 2022-01-26 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
JP7010638B2 (ja) * 2017-09-26 2022-01-26 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
JP6886379B2 (ja) * 2017-09-28 2021-06-16 Towa株式会社 保持部材、保持部材の製造方法、検査装置及び切断装置
WO2019111394A1 (ja) * 2017-12-07 2019-06-13 株式会社Fuji 情報管理装置及び情報管理方法
JP7102271B2 (ja) * 2018-07-17 2022-07-19 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
JP7146352B2 (ja) * 2018-12-10 2022-10-04 株式会社ディスコ 試験装置
EP3920677B1 (en) * 2019-02-01 2023-04-05 Fuji Corporation Work machine
JP7299728B2 (ja) * 2019-03-22 2023-06-28 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
JP7300353B2 (ja) * 2019-09-13 2023-06-29 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
JP7377655B2 (ja) * 2019-09-19 2023-11-10 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
JP7437987B2 (ja) * 2020-03-23 2024-02-26 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
JP7502108B2 (ja) 2020-07-31 2024-06-18 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
KR102792628B1 (ko) * 2020-11-03 2025-04-07 세메스 주식회사 다이 이송 장치 및 방법
JP7575937B2 (ja) * 2020-12-21 2024-10-30 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
JP7635075B2 (ja) * 2021-05-28 2025-02-25 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
DE102022118873B4 (de) * 2022-07-27 2024-02-08 ASMPT GmbH & Co. KG Verfahren und Vorrichtung zum Entnehmen von Chips von einem Waferfilmframe, Bestücksystem und Computerprogramm
JP2024017960A (ja) * 2022-07-28 2024-02-08 ファスフォードテクノロジ株式会社 ダイボンディング装置、ダイボンディング方法および半導体装置の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960015001A (ko) * 1994-10-07 1996-05-22 가나이 쓰토무 반도체 기판의 제조방법과 피검사체상의 패턴결함을 검사하기 위한 방법 및 장치
JP3744966B2 (ja) * 1994-10-07 2006-02-15 株式会社ルネサステクノロジ 半導体基板の製造方法
JPH11345865A (ja) * 1998-06-01 1999-12-14 Sony Corp 半導体製造装置
JP2000150546A (ja) * 1998-11-16 2000-05-30 Toshiba Corp 電子部品の実装装置及び実装方法
JP2005332982A (ja) * 2004-05-20 2005-12-02 Renesas Technology Corp 半導体装置の製造方法
JP2006138830A (ja) * 2004-11-10 2006-06-01 Nippon Electro Sensari Device Kk 表面欠陥検査装置
JP4624813B2 (ja) * 2005-01-21 2011-02-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体製造装置
JP4830772B2 (ja) * 2006-10-11 2011-12-07 ヤマハ株式会社 半導体チップの検査方法
JP5054949B2 (ja) * 2006-09-06 2012-10-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2008215875A (ja) * 2007-02-28 2008-09-18 Omron Corp 成形体の検査方法およびこの方法を用いた検査装置
US7847927B2 (en) * 2007-02-28 2010-12-07 Hitachi High-Technologies Corporation Defect inspection method and defect inspection apparatus
JP5903229B2 (ja) * 2011-08-30 2016-04-13 ファスフォードテクノロジ株式会社 ダイボンダ及び半導体製造方法
JP2013092661A (ja) * 2011-10-26 2013-05-16 Panasonic Corp 部品実装装置に用いる撮像用照明ユニット及び部品実装装置
JP5438165B2 (ja) * 2012-06-13 2014-03-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6266275B2 (ja) * 2013-09-09 2018-01-24 ファスフォードテクノロジ株式会社 ダイボンダ及びボンディング方法

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KR20170076545A (ko) 2017-07-04
JP2017117916A (ja) 2017-06-29
TWI624887B (zh) 2018-05-21
TW201735209A (zh) 2017-10-01
CN106920762A (zh) 2017-07-04
CN106920762B (zh) 2020-03-10

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