JP6676170B2 - 時間遅延フィルタ - Google Patents
時間遅延フィルタ Download PDFInfo
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- JP6676170B2 JP6676170B2 JP2018532034A JP2018532034A JP6676170B2 JP 6676170 B2 JP6676170 B2 JP 6676170B2 JP 2018532034 A JP2018532034 A JP 2018532034A JP 2018532034 A JP2018532034 A JP 2018532034A JP 6676170 B2 JP6676170 B2 JP 6676170B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/30—Time-delay networks
- H03H7/32—Time-delay networks with lumped inductance and capacitance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/09—Filters comprising mutual inductance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1708—Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
- H03H7/1775—Parallel LC in shunt or branch path
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/30—Time-delay networks
- H03H7/32—Time-delay networks with lumped inductance and capacitance
- H03H7/325—Adjustable networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/30—Time-delay networks
- H03H7/34—Time-delay networks with lumped and distributed reactance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/30—Time-delay networks
- H03H7/34—Time-delay networks with lumped and distributed reactance
- H03H7/345—Adjustable networks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H2001/0021—Constructional details
- H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
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Description
本出願は、2015年12月16日に出願された米国仮出願第62/268,408号の利益を主張するものであり、その全体が引用により本明細書に援用される。
図1に示すように、時間遅延フィルタ100は、1またはそれ以上のLC共振器110を含む。時間遅延フィルタ100は、フィルタ内結合素子120および/または入力整合素子130をさらに含むことができる。時間遅延フィルタ100は、追加的または代替的に、任意の数のLC共振器110を含むことができる(例えば、LC共振器110のセットは、単一のLC共振器のみを含むものであってもよい)。時間遅延フィルタ100は、追加的または代替的に、時間遅延の生成を補助するかまたは時間遅延の生成に寄与する、1または複数のLC共振器110に結合される任意の適当なコンポーネントを含むことができ、それには、受動的または能動的コンポーネント(例えば、キャパシタ、トランジスタ、スイッチなど)、内蔵コンポーネント(例えば、導電層および/またはトレース)または任意のその他の適切なコンポーネントが含まれる。
代替的には、LC共振器は、任意の適切な方法で周波数の関数として変化する任意の適切な全インピーダンスを提供するために互いにネットワーク化された回路素子を含むことができる。
Claims (20)
- 時間遅延フィルタにおいて、
・第1の絶縁層を含む基板であって、前記第1の絶縁層が第1の表面および第2の表面を含み、前記第2の表面が前記第1の表面と実質的に平行である、基板と、
・誘導性素子に結合された容量性素子を含む共振器であって、前記誘導性素子が、
−前記第1の絶縁層の第1の表面に結合された第1の導電領域と、
−前記第1の絶縁層の第2の表面に結合された第2の導電領域と、
−前記第1および第2の導電領域に電気的に結合され、前記第1および第2の導電領域間に延在する第1のビアと、
−前記第1の導電領域および前記容量性素子の第1の部分に電気的に結合され、前記第1の導電領域と前記容量性素子の第1の部分との間に延在する第2のビアと、
−前記第2の導電領域および前記容量性素子の第2の部分に電気的に結合され、前記第2の導電領域と前記容量性素子の第2の部分との間に延在する第3のビアとを含み、前記第1の導電領域、前記第1のビア、前記第2の導電領域、前記第2のビア、前記容量性素子および前記第3のビアがループを形成する、共振器と、
・前記共振器の第1の導電領域に電気的に結合された第1の結合点と、
・前記共振器の第2の導電領域に電気的に結合された第2の結合点とを備えることを特徴とする時間遅延フィルタ。 - 請求項1に記載の時間遅延フィルタにおいて、
前記容量性素子の第1の部分が第1の導電性平面領域を含み、前記容量性素子の第2の部分が第2の導電性平面領域を含み、前記第1および第2の部分が実質的に平行であることを特徴とする時間遅延フィルタ。 - 請求項2に記載の時間遅延フィルタにおいて、
前記容量性素子の第1および第2の面が、前記基板の誘電体層によって分離され、前記誘電体層が酸化ハフニウムを含むことを特徴とする時間遅延フィルタ。 - 請求項2に記載の時間遅延フィルタにおいて、
前記第1の導電性平面領域が第1および第2のサブ領域を含み、前記第1および第2のサブ領域が電気的に絶縁され、前記第2の導電性平面領域が第3および第4のサブ領域を含み、前記第3および第4のサブ領域が電気的に絶縁され、前記第3のサブ領域の投影領域が、前記第1のサブ領域の投影領域と重なり、かつ前記第2のサブ領域の投影領域と重なることを特徴とする時間遅延フィルタ。 - 請求項4に記載の時間遅延フィルタにおいて、
第1および第2のタップ点をさらに備え、前記第1のタップ点が前記第3のサブ領域に電気的に結合され、前記第2のタップ点が前記第2のサブ領域に電気的に結合されていることを特徴とする時間遅延フィルタ。 - 請求項5に記載の時間遅延フィルタにおいて、
前記基板が、前記第1の表面と第2の表面との間に導電層を含み、前記導電層が、前記第1の表面と第2の表面との間の点で前記第1のビアに電気的に結合されており、前記導電層に電気的に結合された第3のタップ点をさらに備えることを特徴とする時間遅延フィルタ。 - 請求項1に記載の時間遅延フィルタにおいて、
前記第1の導電領域が、前記第1の表面の第1の領域上に延在するストリップインダクタを含み、前記第2の導電領域が、前記第2の表面の第2の領域上に延在する接地面を含み、前記第2領域が前記第1領域よりも大きいことを特徴とする時間遅延フィルタ。 - 請求項1に記載の時間遅延フィルタにおいて、
前記基板が、前記絶縁層の第1の表面と第2の表面との間に導電層を含み、前記導電層が、前記第1の表面と第2の表面との間の点で前記第1のビアに電気的に接続されており、前記導電層に電気的に接続された第1のタップ点をさらに備えることを特徴とする時間遅延フィルタ。 - 請求項8に記載の時間遅延フィルタにおいて、
前記第1の表面と前記第2の表面との間の第2の点で前記第1のビアに電気的に接続された第2のタップ点と、
第1のスイッチ状態にあるときに、前記第1のタップ点と前記第1の結合点とを抵抗結合し、第2のスイッチ状態にあるときに、前記第2のタップ点と前記第1の結合点とを抵抗結合するスイッチとをさらに備えることを特徴とする時間遅延フィルタ。 - 時間遅延フィルタにおいて、
・第1の表面と、前記第1の表面の反対側の第2の表面とを含む基板であって、前記第1の表面が第1の導電領域を含む、基板と、
・前記基板に結合された第1のLC共振器であって、
−第1の結合点と、
−前記第1の結合点と前記第1の導電領域との間に電気的に結合された第1の容量性素子と、
−前記第1の結合点と前記第1の導電領域との間に電気的に結合され、第1および第2のインダクタタップを有する第1の誘導性素子とを含む、第1のLC共振器と、
・第1のスイッチ状態にあるときに前記第1のインダクタタップを前記第1の結合点に結合し、第2のスイッチ状態にあるときに前記第2のインダクタタップを前記第1の結合点に結合する第1のスイッチであって、前記誘導性素子が、前記第1のスイッチが前記第1のスイッチ状態にあるときに第1のインダクタンスを有し、前記第1のスイッチが前記第2のスイッチ状態にあるときに第2のインダクタンスを有する、第1のスイッチと、
・前記基板に結合された第2のLC共振器であって、
−第2の結合点と、
−前記第2の結合点と前記第1の導電領域との間に電気的に結合された第2の容量性素子と、
−前記第2の結合点と前記第1の導電領域との間に電気的に結合された第2の誘導性素子とを含む、第2のLC共振器とを備え、
時間遅延フィルタが、前記第1の結合点で入力される信号に対して、前記第2の結合点で出力される信号を遅延させることを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記第1の誘導性素子が、
・前記第2の表面に結合された第2の導電領域と、
・前記第1の導電領域および第2の導電領域に電気的に接続され、前記第1の導電領域と第2の導電領域との間に延在する第1のビアと、
・前記第1の導電領域および前記第1の容量性素子の第1の部分に電気的に接続され、前記第1の導電領域と前記第1の容量性素子の第1の部分との間に延在する第2のビアであって、前記第1および第2のインダクタタップが抵抗結合された第2のビアと、
・前記第2の導電領域および前記第1の容量性素子の第2の部分に電気的に接続され、前記第2の導電領域と前記第1の容量性素子の第2の部分との間に延在する第3のビアとを備え、
前記第1の導電領域、前記第1のビア、前記第2の導電領域、前記第2のビア、前記第1の容量性素子および前記第3のビアがループを規定することを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記第1および第2のLC共振器が、入力整合素子と出力整合素子との間に並列に電気的に接続されていることを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記第1および第2のLC共振器が同一の周波数応答を有することを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記第1の結合点と前記第2の結合点との間に結合されたチューナブルキャパシタをさらに備えることを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記第1の結合点および第2の結合点が抵抗結合されていることを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
動作中に、前記第1のLC共振器の第1の誘導性素子が、前記第2のLC共振器の第2の誘導性素子に電磁結合されることを特徴とする時間遅延フィルタ。 - 請求項16に記載の時間遅延フィルタにおいて、
前記第1の結合点と前記第2の結合点との間に電気的に結合された容量性素子をさらに備えることを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記第1の誘導性素子が、並列に接続された複数の誘導性小素子を含み、前記複数の誘導性小素子が編組構造であることを特徴とする時間遅延フィルタ。 - 請求項10に記載の時間遅延フィルタにおいて、
前記基板に結合されるとともに、前記第1の導電領域に電気的に結合された第3のLC共振器であって、第3の誘導性素子、第3の容量性素子および第3の結合点を含む第3のLC共振器と、
前記基板に結合されるとともに、前記第1の導電領域に電気的に結合された第4のLC共振器であって、第4の誘導性素子、第4の容量性素子および第4の結合点を含む第4のLC共振器とをさらに備えることを特徴とする時間遅延フィルタ。 - 請求項19に記載の時間遅延フィルタにおいて、
第1のキャパシタが前記第1の結合点と第4の結合点との間に結合され、前記第1の誘導性素子と第2の誘導性素子が動作中に電磁結合され、第2のキャパシタが前記第2の結合点と第3の結合点との間に結合され、前記第3の誘導性素子と第4の誘導性素子が動作中に電磁結合されることを特徴とする時間遅延フィルタ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562268408P | 2015-12-16 | 2015-12-16 | |
US62/268,408 | 2015-12-16 | ||
PCT/US2016/067352 WO2017106766A1 (en) | 2015-12-16 | 2016-12-16 | Time delay filters |
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