JP6649700B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP6649700B2
JP6649700B2 JP2015107672A JP2015107672A JP6649700B2 JP 6649700 B2 JP6649700 B2 JP 6649700B2 JP 2015107672 A JP2015107672 A JP 2015107672A JP 2015107672 A JP2015107672 A JP 2015107672A JP 6649700 B2 JP6649700 B2 JP 6649700B2
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Japan
Prior art keywords
electrode
voltage
conductive layer
electrodes
resistance state
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Expired - Fee Related
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JP2015107672A
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English (en)
Japanese (ja)
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JP2016225364A (ja
JP2016225364A5 (enExample
Inventor
椎本　恒則
恒則 椎本
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to JP2015107672A priority Critical patent/JP6649700B2/ja
Priority to PCT/JP2016/002430 priority patent/WO2016189831A1/en
Priority to KR1020177033165A priority patent/KR20180012261A/ko
Priority to US15/574,771 priority patent/US10340279B2/en
Publication of JP2016225364A publication Critical patent/JP2016225364A/ja
Publication of JP2016225364A5 publication Critical patent/JP2016225364A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326—Application of electric currents or fields, e.g. for electroforming
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2015107672A 2015-05-27 2015-05-27 半導体装置およびその製造方法 Expired - Fee Related JP6649700B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2015107672A JP6649700B2 (ja) 2015-05-27 2015-05-27 半導体装置およびその製造方法
PCT/JP2016/002430 WO2016189831A1 (en) 2015-05-27 2016-05-18 Semiconductor device and method of manufacturing the same
KR1020177033165A KR20180012261A (ko) 2015-05-27 2016-05-18 반도체 디바이스 및 그 제조 방법
US15/574,771 US10340279B2 (en) 2015-05-27 2016-05-18 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015107672A JP6649700B2 (ja) 2015-05-27 2015-05-27 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2016225364A JP2016225364A (ja) 2016-12-28
JP2016225364A5 JP2016225364A5 (enExample) 2018-07-05
JP6649700B2 true JP6649700B2 (ja) 2020-02-19

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JP2015107672A Expired - Fee Related JP6649700B2 (ja) 2015-05-27 2015-05-27 半導体装置およびその製造方法

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Country Link
US (1) US10340279B2 (enExample)
JP (1) JP6649700B2 (enExample)
KR (1) KR20180012261A (enExample)
WO (1) WO2016189831A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019054171A (ja) 2017-09-15 2019-04-04 東芝メモリ株式会社 記憶装置
US11527473B2 (en) 2019-11-12 2022-12-13 Samsung Electronics Co., Ltd. Semiconductor memory device including capacitor
KR102825706B1 (ko) 2019-11-12 2025-06-25 삼성전자주식회사 커패시터를 포함하는 반도체 메모리 장치
WO2023011561A1 (zh) * 2021-08-06 2023-02-09 南方科技大学 存储器
EP4167702A1 (en) * 2021-10-18 2023-04-19 Samsung Electronics Co., Ltd. Non-volatile memory device and method of manufacturing the same
JP2023137598A (ja) * 2022-03-18 2023-09-29 キオクシア株式会社 半導体装置
CN117794233A (zh) * 2022-09-20 2024-03-29 华为技术有限公司 一种存储芯片、其操作方法及电子设备

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7420242B2 (en) * 2005-08-31 2008-09-02 Macronix International Co., Ltd. Stacked bit line dual word line nonvolatile memory
JP5091491B2 (ja) 2007-01-23 2012-12-05 株式会社東芝 不揮発性半導体記憶装置
JP2010225918A (ja) * 2009-03-24 2010-10-07 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US8383512B2 (en) * 2011-01-19 2013-02-26 Macronix International Co., Ltd. Method for making multilayer connection structure
JP5751552B2 (ja) * 2011-03-04 2015-07-22 マクロニクス インターナショナル カンパニー リミテッド 積層した接続レベルを有する集積回路装置用マスク数の低減法
JP5550604B2 (ja) 2011-06-15 2014-07-16 株式会社東芝 三次元半導体装置及びその製造方法
KR101818975B1 (ko) * 2011-10-14 2018-03-02 삼성전자주식회사 수직형 반도체 소자의 제조 방법
JP2013187335A (ja) * 2012-03-07 2013-09-19 Toshiba Corp 半導体装置及びその製造方法
US9099538B2 (en) * 2013-09-17 2015-08-04 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3D device
US8970040B1 (en) * 2013-09-26 2015-03-03 Macronix International Co., Ltd. Contact structure and forming method
JP2015076556A (ja) * 2013-10-10 2015-04-20 ソニー株式会社 メモリ装置、書込方法、読出方法
US9455265B2 (en) * 2013-11-27 2016-09-27 Macronix International Co., Ltd. Semiconductor 3D stacked structure and manufacturing method of the same

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Publication number Publication date
JP2016225364A (ja) 2016-12-28
US10340279B2 (en) 2019-07-02
US20180102371A1 (en) 2018-04-12
KR20180012261A (ko) 2018-02-05
WO2016189831A1 (en) 2016-12-01

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