JP6600518B2 - バスシステム - Google Patents

バスシステム Download PDF

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Publication number
JP6600518B2
JP6600518B2 JP2015189795A JP2015189795A JP6600518B2 JP 6600518 B2 JP6600518 B2 JP 6600518B2 JP 2015189795 A JP2015189795 A JP 2015189795A JP 2015189795 A JP2015189795 A JP 2015189795A JP 6600518 B2 JP6600518 B2 JP 6600518B2
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Japan
Prior art keywords
master
slave
dummy
master device
bus
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JP2015189795A
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English (en)
Japanese (ja)
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JP2017068345A5 (enExample
JP2017068345A (ja
Inventor
敏幸 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2015189795A priority Critical patent/JP6600518B2/ja
Priority to US15/217,982 priority patent/US20170091130A1/en
Priority to CN201610842312.6A priority patent/CN106557446B/zh
Publication of JP2017068345A publication Critical patent/JP2017068345A/ja
Publication of JP2017068345A5 publication Critical patent/JP2017068345A5/ja
Application granted granted Critical
Publication of JP6600518B2 publication Critical patent/JP6600518B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
JP2015189795A 2015-09-28 2015-09-28 バスシステム Active JP6600518B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015189795A JP6600518B2 (ja) 2015-09-28 2015-09-28 バスシステム
US15/217,982 US20170091130A1 (en) 2015-09-28 2016-07-23 Bus system
CN201610842312.6A CN106557446B (zh) 2015-09-28 2016-09-22 总线系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015189795A JP6600518B2 (ja) 2015-09-28 2015-09-28 バスシステム

Publications (3)

Publication Number Publication Date
JP2017068345A JP2017068345A (ja) 2017-04-06
JP2017068345A5 JP2017068345A5 (enExample) 2018-06-21
JP6600518B2 true JP6600518B2 (ja) 2019-10-30

Family

ID=58407215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015189795A Active JP6600518B2 (ja) 2015-09-28 2015-09-28 バスシステム

Country Status (3)

Country Link
US (1) US20170091130A1 (enExample)
JP (1) JP6600518B2 (enExample)
CN (1) CN106557446B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10073939B2 (en) 2015-11-04 2018-09-11 Chronos Tech Llc System and method for application specific integrated circuit design
US11550982B2 (en) 2015-11-04 2023-01-10 Chronos Tech Llc Application specific integrated circuit interconnect
US9977853B2 (en) 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit link
US9977852B2 (en) 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit interconnect
US10331835B2 (en) 2016-07-08 2019-06-25 Chronos Tech Llc ASIC design methodology for converting RTL HDL to a light netlist
US10181939B2 (en) 2016-07-08 2019-01-15 Chronos Tech Llc Systems and methods for the design and implementation of an input and output ports for circuit design
US10637592B2 (en) 2017-08-04 2020-04-28 Chronos Tech Llc System and methods for measuring performance of an application specific integrated circuit interconnect
KR102385541B1 (ko) * 2017-09-29 2022-04-11 삼성전자주식회사 버스 시스템
CN108168548B (zh) * 2018-02-13 2022-03-15 南京师范大学 一种通过机器学习算法与模型辅助的行人惯性导航系统和方法
US11087057B1 (en) 2019-03-22 2021-08-10 Chronos Tech Llc System and method for application specific integrated circuit design related application information including a double nature arc abstraction
JP7466329B2 (ja) * 2020-02-19 2024-04-12 キヤノン株式会社 制御装置、システム、リソグラフィ装置、物品の製造方法、制御方法、およびプログラム
CN113542090B (zh) * 2020-04-14 2023-07-14 宁波弘讯科技股份有限公司 一种EtherCAT主从站一体网桥控制器及控制方法
WO2022160206A1 (zh) * 2021-01-28 2022-08-04 华为技术有限公司 一种片上系统异常处理方法、片上系统及其装置
TWI817831B (zh) * 2022-11-16 2023-10-01 旺玖科技股份有限公司 具有建立動態位址表的串列通訊匯流排系統及其控制方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0660015A (ja) * 1992-06-08 1994-03-04 Mitsubishi Electric Corp 情報処理装置
US5579492A (en) * 1993-11-01 1996-11-26 Motorola, Inc. Data processing system and a method for dynamically ignoring bus transfer termination control signals for a predetermined amount of time
JP4198376B2 (ja) * 2002-04-02 2008-12-17 Ｎｅｃエレクトロニクス株式会社 バスシステム及びバスシステムを含む情報処理システム
JP4055903B2 (ja) * 2003-12-26 2008-03-05 シャープ株式会社 バス通信システム
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법
JP2010140361A (ja) * 2008-12-12 2010-06-24 Fujitsu Microelectronics Ltd コンピュータシステム及び異常検出回路
JP5856434B2 (ja) * 2011-10-25 2016-02-09 ルネサスエレクトロニクス株式会社 バス接続回路、半導体装置及びバス接続回路の動作方法
US20140025852A1 (en) * 2012-07-19 2014-01-23 Lsi Corporation Configurable Response Generator for Varied Regions of System Address Space
CN103810074B (zh) * 2012-11-14 2017-12-29 华为技术有限公司 一种片上系统芯片及相应的监控方法
CN103217930B (zh) * 2013-05-02 2016-01-27 浙江中控技术股份有限公司 一种工业控制器间的数据交互系统
US9342422B2 (en) * 2013-11-07 2016-05-17 International Business Machines Corporation Selectively coupling a PCI host bridge to multiple PCI communication paths
US9804942B2 (en) * 2014-06-10 2017-10-31 Analog Devices, Inc. Safety node in interconnect data buses

Also Published As

Publication number Publication date
CN106557446B (zh) 2021-06-08
CN106557446A (zh) 2017-04-05
JP2017068345A (ja) 2017-04-06
US20170091130A1 (en) 2017-03-30

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