JP6530234B2 - 電子部品搭載装置及び電子部品の搭載方法 - Google Patents
電子部品搭載装置及び電子部品の搭載方法 Download PDFInfo
- Publication number
- JP6530234B2 JP6530234B2 JP2015101394A JP2015101394A JP6530234B2 JP 6530234 B2 JP6530234 B2 JP 6530234B2 JP 2015101394 A JP2015101394 A JP 2015101394A JP 2015101394 A JP2015101394 A JP 2015101394A JP 6530234 B2 JP6530234 B2 JP 6530234B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- holding
- semiconductor chip
- tool
- holding tool
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015101394A JP6530234B2 (ja) | 2015-05-18 | 2015-05-18 | 電子部品搭載装置及び電子部品の搭載方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015101394A JP6530234B2 (ja) | 2015-05-18 | 2015-05-18 | 電子部品搭載装置及び電子部品の搭載方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016219552A JP2016219552A (ja) | 2016-12-22 |
| JP2016219552A5 JP2016219552A5 (enExample) | 2018-01-18 |
| JP6530234B2 true JP6530234B2 (ja) | 2019-06-12 |
Family
ID=57581499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015101394A Active JP6530234B2 (ja) | 2015-05-18 | 2015-05-18 | 電子部品搭載装置及び電子部品の搭載方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6530234B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6323746B2 (ja) * | 2014-02-19 | 2018-05-16 | パナソニックIpマネジメント株式会社 | 加圧ツール及び電子部品搭載装置 |
| WO2020031244A1 (ja) * | 2018-08-06 | 2020-02-13 | 株式会社島津製作所 | 搬送装置 |
| TWI765762B (zh) * | 2020-12-25 | 2022-05-21 | 梭特科技股份有限公司 | 角落或側邊接觸的無衝擊力固晶方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204327A (ja) * | 1995-01-20 | 1996-08-09 | Sony Corp | 実装装置 |
| JP3561089B2 (ja) * | 1996-07-15 | 2004-09-02 | 株式会社東芝 | 半導体チップの実装方法およびその装置 |
| JP3399324B2 (ja) * | 1997-11-10 | 2003-04-21 | 松下電器産業株式会社 | 半田バンプ付電子部品の熱圧着方法 |
| CN101894774B (zh) * | 2005-03-17 | 2012-02-15 | 松下电器产业株式会社 | 电子部件安装方法和电子部件安装装置 |
| JP4974982B2 (ja) * | 2008-09-09 | 2012-07-11 | パナソニック株式会社 | 実装装置 |
| JP2010064172A (ja) * | 2008-09-10 | 2010-03-25 | Seiko Epson Corp | 吸引保持ハンド、搬送装置の制御方法、搬送装置および検査装置 |
| JP2010153672A (ja) * | 2008-12-26 | 2010-07-08 | Nec Corp | 半導体装置の製造装置およびその製造方法 |
-
2015
- 2015-05-18 JP JP2015101394A patent/JP6530234B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2016219552A (ja) | 2016-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101419690B1 (ko) | 반도체 칩들의 열 압착 본딩 | |
| US9120169B2 (en) | Method for device packaging | |
| US8318537B2 (en) | Flip chip interconnection having narrow interconnection sites on the substrate | |
| USRE44355E1 (en) | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density | |
| EP1777738A1 (en) | Component mounting method and component mounting apparatus | |
| US10014272B2 (en) | Die bonding with liquid phase solder | |
| US7901983B2 (en) | Bump-on-lead flip chip interconnection | |
| CN102254888A (zh) | 印刷电路板单元制造方法及设备、电子部件及其制造方法 | |
| JP6530234B2 (ja) | 電子部品搭載装置及び電子部品の搭載方法 | |
| JP4154397B2 (ja) | 電子装置及びスタンドオフ部材及び電子装置の製造方法 | |
| JP2010177604A (ja) | 半導体製造方法及び製造装置 | |
| WO2001031699A1 (en) | Advanced flip-chip join package | |
| JP2011151179A (ja) | ボンディング装置 | |
| JP6601055B2 (ja) | プリント配線板、電子機器及び実装方法 | |
| CN110164781B (zh) | 电子封装件的制法 | |
| TWI515811B (zh) | 拉伸焊料凸塊的方法 | |
| KR101349987B1 (ko) | 용융 금속 토출 장치 | |
| JP3855874B2 (ja) | 電子部品の実装方法、icチップの実装方法およびicチップ | |
| KR20090069825A (ko) | 솔더 범프 제작용 템플릿 | |
| JP2011044530A (ja) | はんだ接合方法およびはんだ接合装置 | |
| JP2837145B2 (ja) | チップ部品と基板との接続方法および接続装置 | |
| JPH04338657A (ja) | チップ部品と基板との接続方法 | |
| JP2000183114A (ja) | ボンディング装置 | |
| KR100955603B1 (ko) | 솔더범프 형성장치 및 방법 | |
| CN115101434A (zh) | 封装结构制作方法和芯片防翘曲装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20171130 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20171130 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180926 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181009 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181205 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190423 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190516 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6530234 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |