JP6523431B2 - 抵抗変化素子アレイに動的にアクセスし、プログラミングする方法 - Google Patents
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Description
本出願は、本出願の譲受人に譲渡され、参照によりその全体が本明細書に組み込まれる、2014年8月12日に出願された、米国特許出願公開第14/457,520号明細書の35U.S.C.§120に基づく利益を主張する。
あるいは、抵抗変化素子の状態は、例えば、抵抗変化素子に固定直流電流を流し、抵抗変化素子の両端に生じる電圧を測定することによっても判定することができる。どちらの場合も、抵抗変化素子に印加される電気刺激は、素子の抵抗状態を変化させないように制限される。このようにして、READ動作は、抵抗変化メモリ素子の状態を決定することができる。
残りのワード線(WL[1]−WL[y])は、接地(0V)に駆動され、残りのビット線(BL[1]−BL[x])は、WL[0]に供給される同じ電圧で駆動される。このようにして、選択されたビット線(BL[0])の残りのセル、すなわち、CELL01−CELL0y内の選択ダイオードは、バイアスされないままであり、各セルでは、関連するワード線および関連するビット線の両方で、0Vが観測される。同様に、選択されたワード線(WL[0])の残りのセル、すなわちCELL10−CELLx0内の選択ダイオードもバイアスされないままであり、それらのセルのそれぞれでは、関連するワード線および関連するビット線の両方で、印加されたプログラミングまたはREAD電圧が観測される。最後に、アレイ内の残りのセル、すなわち、CELL11−CELLxy内の選択ダイオードは逆バイアスされ、それらのセルのそれぞれでは、関連するワード線で0Vが、および関連するビット線で印加されたプログラミング電圧またはREAD電圧が、観測される。このようにして、D00のみが順バイアスされ、印加されたプログラミングまたはREAD電圧(または、電流)が、選択された抵抗変化素子SW00上にのみ印加される。
Claims (31)
- 抵抗変化素子アレイ内の少なくとも1つの抵抗変化素子の抵抗状態を判定する方法であって、
抵抗変化素子アレイを提供する工程であって、前記抵抗変化素子アレイが、
複数のワード線と、
複数のビット線と、
複数の抵抗変化素子であって、各抵抗変化素子が第1の端子と第2の端子とを有し、各抵抗変化素子の前記第1の端子がワード線と電気的に結合し、各抵抗変化素子の前記第2の端子がビット線と電気的に結合する、複数の抵抗変化素子と、
を備える、工程と、
前記抵抗変化素子アレイ内の前記ビット線のすべてと前記ワード線のすべてとを、事前選択した電圧レベルに同時に充電する工程と、
前記抵抗変化素子アレイ内の1つのワード線を選択することと、前記選択されたワード線を浮動させることを可能にして、一方で、他のワード線のすべてと前記ビット線のすべてを接地に駆動する工程と、
前記選択されたワード線をそれらの抵抗変化素子を介して放電して、少なくとも1つの抵抗変化素子に対して少なくとも1つの読み取り電流値を測定する場合に前記選択されたワード線と電気的に接続するそれらの抵抗変化素子を通る電流を観測する工程と、
前記少なくとも1つの読み取り電流値から、少なくとも1つの抵抗変化素子の抵抗状態を判定する工程と、
を含むことを特徴とする方法。 - 前記選択されたワード線がまた、少なくとも1つの抵抗基準素子を介して放電することを特徴とする請求項1に記載の方法。
- 少なくとも1つの抵抗変化素子の前記抵抗状態が、少なくとも1つの読み取り電流値を、前記少なくとも1つの抵抗基準素子を介して測定された電流値と比較することによって判定されることを特徴とする請求項2に記載の方法。
- 前記選択されたワード線と電気的に結合するすべての抵抗変化素子の前記抵抗状態が、同時に判定されることを特徴とする請求項1に記載の方法。
- 比較的高い読み取り電流値が第1の論理状態に対応し、比較的低い読み取り電流値が第2の論理状態に対応することを特徴とする請求項1に記載の方法。
- 前記抵抗変化素子が2端子ナノチューブスイッチング素子であることを特徴とする請求項1に記載の方法。
- 前記2端子ナノチューブスイッチング素子がナノチューブ織物を備えることを特徴とする請求項6に記載の方法。
- 前記抵抗変化素子が金属酸化物メモリ素子であることを特徴とする請求項1に記載の方法。
- 前記抵抗変化素子が相変化メモリ素子であることを特徴とする請求項1に記載の方法。
- 前記抵抗変化素子アレイがメモリアレイであることを特徴とする請求項1に記載の方法。
- 抵抗変化素子アレイ内の少なくとも1つの抵抗変化素子の抵抗状態を調整する方法であって、
抵抗変化素子アレイを提供する工程であって、前記抵抗変化素子アレイが、
複数のワード線と、
複数のビット線と、
複数の抵抗変化素子であって、各抵抗変化素子が第1の端子と第2の端子とを有し、各抵抗変化素子の前記第1の端子がワード線と電気的に結合し、各抵抗変化素子の前記第2の端子がビット線と電気的に結合する、複数の抵抗変化素子と、
を備える工程と、
前記抵抗変化素子アレイ内の前記ビット線のすべてと前記ワード線のすべてとを、事前選択した電圧レベルに同時に充電する工程と、
前記抵抗変化素子アレイ内の1つのワード線を選択することと、前記選択したワード線を接地に駆動して、一方、他のワード線のすべてと前記ビット線のすべてとを浮動することを可能にする工程と、
それらの抵抗変化素子を介して前記選択されたワード線と電気的に結合するそれらの抵抗変化素子と電気的に結合するそれらのビット線を放電して、少なくとも1つの抵抗変化素子を通る少なくとも1つのプログラミング電流をもたらす工程と、
を含み、
前記少なくとも1つのプログラミング電流が、少なくとも1つの抵抗変化素子の電気抵抗を、第1の抵抗状態から第2の抵抗状態に調整することを特徴とする方法。 - 前記第1の抵抗状態が前記第2の抵抗状態より低いことを特徴とする請求項11に記載の方法。
- 前記第1の抵抗状態が前記第2の抵抗状態より高いことを特徴とする請求項11に記載の方法。
- 前記選択されたワード線と電気的に結合するすべての抵抗変化素子の抵抗状態が、同時に調整されることを特徴とする請求項11に記載の方法。
- 前記第1の抵抗状態が第1の論理値に対応し、前記第2の抵抗状態が第2の論理値に対応することを特徴とする請求項11に記載の方法。
- 前記選択されたワード線と電気的に結合する抵抗変化素子のすべてが、前記選択されたワード線が放電された後に同じ論理値でプログラミングされることを特徴とする請求項15に記載の方法。
- 前記抵抗変化素子が2端子ナノチューブスイッチング素子であることを特徴とする請求項11に記載の方法。
- 前記2端子ナノチューブスイッチング素子がナノチューブ織物を備えることを特徴とする請求項17に記載の方法。
- 前記抵抗変化素子が金属酸化物メモリ素子であることを特徴とする請求項11に記載の方法。
- 前記抵抗変化素子が相変化メモリ素子であることを特徴とする請求項11に記載の方法。
- 前記抵抗変化素子アレイがメモリアレイであることを特徴とする請求項11に記載の方法。
- 抵抗変化素子アレイ内の単一抵抗変化素子の抵抗状態を調整する方法であって、
抵抗変化素子アレイを提供する工程であって、前記抵抗変化素子アレイが、
複数のワード線と、
複数のビット線と、
複数の抵抗変化素子であって、各抵抗変化素子が第1の端子と第2の端子とを有し、各抵抗変化素子の前記第1の端子がワード線と電気的に結合し、各抵抗変化素子の前記第2の端子がビット線と電気的に結合する、複数の抵抗変化素子と、
を備える工程と、
前記抵抗変化素子アレイ内の前記ビット線のすべてと前記ワード線のすべてとを、事前選択した電圧レベルに同時に充電する工程と、
前記抵抗変化素子アレイ内の1つのワード線と1つのビット線とを選択することと、前記選択されたワード線を浮動させることを可能にして、前記選択されたビット線を接地に駆動して、一方、他のワード線のすべてを接地に駆動して、他のビット線のすべてを電流制限経路を介して接地する工程と、
前記選択されたワード線および前記選択されたビット線と電気的に結合する単一の抵抗変化素子を介して前記選択されたワード線を放電して、前記単一の抵抗変化素子を通るプログラミング電流をもたらす工程と、
を含み、
前記プログラミング電流が、前記単一の抵抗変化素子の電気抵抗を第1の抵抗状態から第2の抵抗状態に調整することを特徴とする方法。 - 前記第1の抵抗状態が前記第2の抵抗状態より低いことを特徴とする請求項22に記載の方法。
- 前記第1の抵抗状態が前記第2の抵抗状態より高いことを特徴とする請求項22に記載の方法。
- 前記第1の抵抗状態が第1の論理値に対応し、前記第2の抵抗状態が第2の論理値に対応することを特徴とする請求項22に記載の方法。
- 前記電流制限経路は、選択されていない抵抗変化素子を通る放電電流が、前記選択されていない抵抗変化素子の抵抗状態を調整するのに充分大きくならないようにするのに充分であることを特徴とする請求項22に記載の方法。
- 前記抵抗変化素子が2端子ナノチューブスイッチング素子であることを特徴とする請求項22に記載の方法。
- 前記2端子ナノチューブスイッチング素子がナノチューブ織物を備えることを特徴とする請求項27に記載の方法。
- 前記抵抗変化素子が金属酸化物メモリ素子であることを特徴とする請求項22に記載の方法。
- 前記抵抗変化素子が相変化メモリ素子であることを特徴とする請求項22に記載の方法。
- 前記抵抗変化素子アレイがメモリアレイであることを特徴とする請求項22に記載の方法。
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