WO2016068911A1

WO2016068911A1 - Resistive memory device

Info

Publication number: WO2016068911A1
Application number: PCT/US2014/062912
Authority: WO
Inventors: James S. Ignowski; Jacquelyn M. INGEMI; Brent Buchanan
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2014-10-29
Filing date: 2014-10-29
Publication date: 2016-05-06
Also published as: TW201629969A

Abstract

A resistive memory device includes a plurality of arrays of resistive memory cells and a plurality of memory access circuits. A different one of the memory access circuits is coupled to each of the arrays. Each of the memory access circuits includes control circuitry to read and write the resistive memory cells of the array to which the memory access circuit is coupled, and a programmable element to vary a parameter of the control circuitry. Operation of the control circuitry for accessing the resistive memory cells is changed by varying the parameter.

Description

RESISTIVE MEMORY DEVICE BACKGROUND

[0001] Resistive memories are data storage devices that record information as a change in the resistance of a storage cell. Resistive memory provides nonvolatile storage, and resistive memory cells may be small relative to storage cells constructed using other memory technologies. Accordingly, resistive memory technologies have the potential to allow for production of higher density storage at a lower cost than conventional memory technologies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0003] Figure 1 shows a block diagram of a resistive memory device that includes programmable parameters for optimizing resistive memory cell access in accordance with various examples;

[0004] Figure 2 shows a block diagram of an array of resistive memory cells and associated access control circuitry in accordance with various examples;

[0005] Figures 3-4 show flow diagrams for methods for adjusting parameters of a resistive memory device that that affect resistive memory cell access in accordance with various examples;

[0006] Figure 5 shows a block diagram of a system for adjusting parameters of a resistive memory device that that affect resistive memory cell access in accordance with various examples; and

[0007] Figure 6 shows a block diagram of a system for testing and adjusting parameters of a resistive memory device in accordance with various examples.

DETAILED DESCRIPTION

[0008] Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, different companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to... ." Also, the term "couple" or "couples" is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.

[0009] In a resistive memory device, the electrical characteristics (e.g., high and low state resistances, voltage thresholds, current thresholds, etc.) of resistive memory cells can vary widely. To accommodate the variation, conventional resistive memory devices provide large guard bands in the memory cell sensing and driving circuitry. The resistive memory device disclosed herein eliminates the need for such large guard banding by programmatically adapting the control circuitry of the device to the resistive memory cells.

[0010] In the resistive memory device disclosed herein, the resistive memory cells are subdivided into geographically distinct arrays, and each array is serviced by dedicated drive/sense circuitry. While the electrical characteristics across a number of arrays may vary substantially, the electrical characteristics of resistive memory cells in the same array tend to be similar. The resistive memory device disclosed herein leverages this similarity by including adaptive elements in the drive/sense circuitry that allow the access control of each array's memory cells to be tailored to the electrical characteristics of the array's cells. Based on the results of testing, the drive/sense circuitry of each resistive memory array of the device is programmed to optimize memory cell access.

[0011] Figure 1 shows a block diagram of a resistive memory device 102 that includes programmable parameters for optimizing resistive memory cell access in accordance with various examples. The resistive memory device 102 includes a plurality of memory cell arrays 1 10 each of which includes a plurality of resistive memory cells. Each of the resistive memory cells may include a resistive memory element and a selector device. The resistive memory element provides resistance that is changeable to represent a data value. A selector device is connected in series with each resistive memory element, and isolates the resistive memory element from other resistive memory cells to reduce the effects of sneak current when, for example, adjacent memory cells are in a low resistance state. The selector devices may be two or three terminal semiconductor devices. Examples of selector devices include: poly-silicon junction diodes, oxide diodes, vanadium dioxide diodes, metal-insulator-metal diodes, mixed ionic-electronic conduction devices, ovonic threshold switches, NPN, PN and Schottky barriers, etc.

[0012] The resistive memory cells of any one of the arrays 1 10 may be proximate one another on the die, and as a result, the electrical characteristics of the resistive memory cells of the array may be similar. The electrical characteristics of the resistive memory cells in one array 1 10 may differ substantially from the electrical characteristics of the resistive memory cells of a different array 1 10. The variance in electrical characteristics may be due to variation in the resistive memory elements and/or variation in the selector devices. For example, the threshold voltage of the selector devices may vary substantially (e.g., by tenths of a volt) across the resistive memory device 102.

[0013] The resistive memory device 102 also includes a plurality of memory access circuits 104. Each of the access circuits 104 is coupled to and services one of the resistive memory cell arrays 1 10. Each of the access circuits 104 include control circuitry 106 that generate the signals that read and write the resistive memory cells of the array 1 10 to which the access circuit 104 is coupled.

[0014] The control circuitry 106 includes one or more programmable elements 108. The programmable element 108 provides for adjustment of the control circuitry 106 at device manufacture or over the operational life of the device 102. Accordingly, the operation of the control circuitry 106 can be adjusted by changing a value provided to the control circuitry 106 by the programmable element. For example, if the electrical characteristics of the resistive memory cells of the array 1 10 coupled to the access circuits 104 dictate use of a different read or write current or voltage than the control circuitry 106 is set to provide, then the programmable element 108 can be written to adjust the read or write current or voltage to a value that is more optimal for the resistive memory cells. Thus, by adjusting the operation of the control circuitry 106, via the programmable elements 108, the resistive memory device 102 can individually compensate for variation in the resistive memory elements and/or the selector devices of each of the arrays 1 10. [0015] In some implementations, the programmable element 108 is a nonvolatile storage element, and may incorporate any of a variety of non-volatile storage. For example, the programmable element 108 may be a fuse, anti-fuse, programmable read-only memory (PROM) cell, electrically-erasable PROM, FLASH memory cell, ferro-electric cell, resistive memory cell, or other non-volatile memory cell or cells. In other implementations, the programmable element 108 is volatile, and operational values are loaded into the programmable element 108 from non-volatile storage in the resistive memory device 102 at initialization. While a single programmable element is shown in Figure 1 , in practice, the control circuitry 106 may include a plurality of programmable elements 108 as needed to provide adjustment of the different parameters to be varied to optimize access of the resistive memory cells controlled by the access circuits 104.

[0016] Figure 2 shows a block diagram of the memory access circuits 104 in accordance with various examples. As shown in Figure 1 , memory access circuits 104 include the control circuitry 106. The control circuitry 106 includes sense circuit 202, drive circuit 204, timing circuit 206, and test circuit 208. The sense circuit 202 detects the storage state of each resistive memory cell accessed by the access circuits 104 to provide reading of stored data. The sense circuit 202 may include amplifiers, comparators, voltage/current generators and other components that have omitted in the interest of clarity. The sense circuit 202 includes one or more programmable elements 108 that provide adjustment of various parameters of the sense circuit 202. For example, the value stored by the programmable element 108 may be changed to adjust current and/or voltage generated by the sense circuit 202 and provided to a resistive memory cell during a read cycle, to adjust thresholds (e.g., logic state thresholds) applied to determine the logic state stored in a resistive memory cell, or to adjust other operational parameters of the sense circuit 202 related to reading the memory cells of the array 1 10 serviced by the access circuits 104.

[0017] The drive circuit 204 generates signals for setting the storage state of each resistive memory cell accessed by the access circuits 104 to a logic state specified for a given value to be stored in the cell. The value to be stored may be provided to the resistive memory device 102 by an external source, such as a processor. The drive circuit 204 may include voltage/current generators and other components that have been omitted in the interest of clarity. The drive circuit 204 includes one or more programmable elements 108 that provide adjustment of various parameters of the drive circuit 204. For example, the value stored by the programmable element 108 may be changed to adjust current and/or voltage generated by the drive circuit 204 and provided to a resistive memory cell during a write cycle, or to adjust other operational parameters of the drive circuit 202 related to writing the memory cells of the array 1 10 serviced by the access circuits 104.

[0018] In various implementations, the sense circuit 202 and/or the drive circuit 204 may include programmable voltage or current generators, programmable delay generators, and/or multi-fingered transistors that allow enabling/disabling of fingers to provide variable gain and drive. Sense and/or drive parameters varied using such programmable components include voltage and current levels for reading and writing the resistive cells, timing parameters and bias levels for the different operating modes of the drive circuit 204 and the sense circuit 202, voltage offset levels, and the like.

[0019] The timing circuit 206 includes circuitry for timing read and/or write operations and/or sub-operations performed by the sense circuit 202 or the drive circuit 204. In some implementations of the control circuitry 106, the timing circuit 206, or portions thereof, may be incorporated in the sense circuit 202 and/or the drive circuit 204. The timing circuit 206 may include counters, clock dividers, delay elements, and other timing generation components. The timing circuit 206 includes one or more programmable elements 108 that provide adjustment of various parameters of the timing circuit 204. For example, a value stored by a programmable element 108 of the timing circuit 206 may be changed to adjust a time over which voltage or current from a resistive memory cell is evaluated to determine the logical state of the cell. Similarly, a value stored by a programmable element 108 may be changed to adjust time over which voltage and/or current is applied to a resistive memory cell to set the cell to a logic state.

[0020] The test circuit 208 monitors the read and/or write operations performed by the sense circuit 202 and the drive circuit 204 over the life of the resistive memory device 102. For example, the test circuit 208 may monitor the voltage/current generated by the resistive memory cells during a read cycle and change one or more values stored in the programmable elements 108 to adjust read/write voltage, current, and/or timing to optimize resistive memory cell operation over the life of the device 102. The test circuit 208 may include analog- to-digital converters, comparators, reference voltage generators, state machines, and/or other circuitry and logic to effect the testing and adjustment of parameters of the control circuitry 106 associated with memory access. The adjustments performed by the test circuit 208 may be tailored to compensate for aging of the resistive memory device 102, effects of temperature variation, and/or other operational performance changes over the life of the life of the device 102.

[0021] In some implementations, the test circuit 208 may acquire and/or accumulate data and forward the data to an external system for analysis. In such implementations, the external system may analyze the data and write the programmable elements 108 to optimize the performance of each resistive memory array 1 10.

[0022] Figures 3-4 show flow diagrams for methods for adjusting parameters of the resistive memory device 102 in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some implementations may perform only some of the actions shown. In some implementations, at least some of the operations of the methods 300 and 400 can be implemented as instructions stored in a storage device and executed by one or more processors.

[0023] In block 302, the resistive memory device 102 is communicatively coupled to a test system (e.g., a manufacturing test system), and the test system writes and reads each of the resistive memory arrays 1 10. In conjunction with writing and reading each array 1 10, the test system and/or the resistive memory device 102 (e.g., test circuit 208) measure various operational parameters of the array 1 10, such as sneak current, read current/voltage, write current/voltage, read threshold, write threshold, etc. [0024] In block 304, the test system analyzes the measured operational parameters and determines whether the performance of each of the arrays 1 10 is in compliance with a predetermined performance standard. If the values indicate that performance of a given array 1 10 is less than optimal (e.g., not within a range of performance specified by the predetermined standard), then the testing system computes adjusted values to be written to the programmable elements 108 of the access circuits 104 controlling the given array. For example, based on the resistance of the array for a given logic state the test system may compute adjusted values for the read thresholds, read voltage or current, write voltage or current, read or write timing, etc.

[0025] In block 306, the test system updates the access control circuits 104 dedicated to controlling each array 1 10 identified as not operating within the limits specified by the predetermined performance standard. The access control circuits 104 are adjusted by writing values to the programmable element(s) 108 of the access control circuits 104 that modify read and/or write operational parameters for the array 1 10.

[0026] In block 406, the manufacturing calibration of the resistive memory device 102 is complete, and the device 102 is operative in the field. The test circuit 208 monitors the performance and activity of each of the arrays 1 10 by acquiring operational and activity data for each array 1 10. If performance of an array 1 10 drifts outside of predetermined acceptable operational performance limits, then the test circuit 208 may adjust the access control circuits 104 by writing values to the programmable element(s) 108 of the control circuitry 106 that modify read and/or write operational parameters for the array 1 10

[0027] Figure 5 shows a block diagram of a system 500 for testing and adjusting performance of the resistive memory device 102 in accordance with various examples. The system 500 may perform the methods 300, 400 disclosed herein. The system 500 includes a resistive memory device 102 to be tested and adjusted, and a resistive memory tester 502 communicatively coupled to the resistive memory device 102. The resistive memory tester 502 may perform operations 302, 304, and 306 of methods 300 and 400. [0028] Figure 6 shows a block diagram of the resistive memory tester 502 in accordance with various examples. The resistive memory tester 502 may include various components and systems that have been omitted from Figure 6 in the interest of clarity. For example, the resistive memory tester 502 may include network adapters, display systems, user interfaces, sockets, probes, and/or fixtures for interfacing with the resistive memory device 102, etc.

[0029] The computer 602 includes processor 602 and storage 604 coupled to the processor 602. The storage 604 is a non-transitory computer-readable storage device. The processor 602 is a general-purpose microprocessor, a digital signal processor, a microcontroller, or other device capable of executing instructions retrieved from a computer-readable storage medium. Processor architectures generally include execution units (e.g., fixed point, floating point, integer, etc.), storage (e.g., registers, memory, etc.), instruction decoding, instruction and data fetching logic, peripherals (e.g., interrupt controllers, timers, direct memory access controllers, etc.), input/output systems (e.g., serial ports, parallel ports, etc.) and various other components and sub-systems.

[0030] The storage 604 includes resistive memory calibration logic 606 that the processor 602 executes to test and adjust the operational performance of each array 1 10 of the resistive memory device 102. The resistive memory calibration logic 606 includes array testing logic 608, array evaluation logic 610, and array control update logic 612. The array testing logic 608 includes instructions that are executed by the processor 102 to write and read each of the resistive memory arrays of the device 102. Various patterns of data and addressing may be provided to test the arrays 1 10.

[0031] The array evaluation logic 610 includes instructions that are executed by the processor 102 to measure parameters of operation (e.g., read/write voltage/current) of each array 1 10 during testing and evaluate the performance of the array based on the measured parameters. For example, the measured voltages and/or currents may be compared to a predetermined standard.

[0032] The array control update logic 612 includes instructions that are executed by the processor 102 to adjust the parameters of operation applied by the control circuitry 106 to access associated resistive memory array 1 10. If results of processing the measured operational parameters of an array 1 10 by the array evaluation logic 610 indicate that the operation and use of the array 1 10 can be improved, then the processor 102 executes the array control update logic 612 to select updated control parameter values for the array 1 10, and writes the updated control parameter values to the programmable element(s) 108 of the control circuitry 106.

[0033] The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

CLAIMS What is claimed is:

1 . A resistive memory device, comprising:

a plurality of arrays of resistive memory cells;

a plurality of memory access circuits, a different one of the memory access circuits coupled to each of the arrays, each of the memory access circuits comprising:

control circuitry to read and write the resistive memory cells of the array to which the memory access circuit is coupled; and a programmable element to vary a parameter of the control circuitry, wherein varying the parameter of the control circuitry changes operation of the control circuitry for accessing each of the resistive memory cells of the array controlled by the memory access circuit.

2. The resistive memory device of claim 1 , wherein the control circuitry comprises sense circuitry to read the resistive memory cells; wherein the programmable element is to adjust at least one of current and voltage applied to the resistive memory cells by the sense circuitry to read the resistive memory cells.

3. The resistive memory device of claim 1 , wherein the control circuitry comprises sense circuitry to read the resistive memory cells; wherein the programmable element is to adjust a logic state threshold applied to the resistive memory cells by the sense circuitry to read the resistive memory cells.

4. The resistive memory device of claim 1 wherein the control circuitry comprises drive circuitry to write the resistive memory cells; wherein the programmable non-volatile element is to adjust at least one of current and voltage applied to the resistive memory cells by the drive circuitry to write the resistive memory cells.

5. The resistive memory device of claim 1 wherein the control circuitry comprises timing circuitry to control timing applied to at least one of reading and writing the resistive memory cells; wherein the programmable element is to adjust the timing applied to at least one of reading and writing the resistive memory cells.

6. The resistive memory device of claim 1 wherein the control circuitry comprises test circuitry to identify a change in operation of the resistive memory cells, and to change a value stored by the programmable element to compensate for the identified change.

7. A method, comprising:

testing performance of a plurality of arrays of resistive memory cells of an integrated circuit using dedicated control circuitry of each of the arrays to access the resistive memory cells of the array; determining, for each of the arrays, whether performance of the array using the control circuitry as configured for the testing complies with a predetermined performance standard;

adjusting operation of the control circuitry for one of the arrays based on the performance of the one of the arrays being noncompliant with the predetermined performance standard; and

writing a programmable element disposed in the control circuitry to effect the adjusting.

8. The method of claim 7, wherein the adjusting comprises changing at least one of current and voltage applied to the resistive memory cells by the control circuitry to read the resistive memory cells.

9. The method of claim 7, wherein the adjusting comprises changing at least one of current and voltage applied to the resistive memory cells by the control circuitry to write the resistive memory cells.

10. The method of claim 7, wherein the adjusting comprises adjust timing generated by the control circuitry to time at least one of read access and write access of the resistive memory cells.

1 1 . The method of claim 7, further comprising:

monitoring performance of the plurality of arrays of resistive memory cells over a lifetime of the integrated circuit;

adjusting operation of the control circuitry for one of the arrays based on the performance of the one of the arrays changing from compliant with the predetermined performance standard to noncompliant with the predetermined performance standard;

writing the programmable element of the control circuitry to effect the adjusting.

12. The method of claim 1 1 , further comprising:

measuring usage of each of the arrays over the lifetime of the integrated circuit; and

adjusting operation of the control circuitry each of the arrays over a lifetime of the integrated circuit based on measured usage of the array.

A system, comprising:

a resistive memory device comprising:

a plurality of arrays of resistive memory cells;

a plurality of memory access circuits, each of the memory access circuits to control a single one of the arrays, each of the memory access circuits comprising:

adaptive control circuitry to read and write the resistive memory cells of the array controlled by the memory access circuit;

a programmable element to adjust a parameter of the adaptive control circuitry; a tester to:

measure values of parameters of each of the arrays of the resistive memory device; and

write, based on the measured values of the parameters, a value to the programmable element of at least one of the memory access circuits to adjust performance of the array controlled by the memory access circuit based on a predetermined performance standard.

14. The system of claim 13, wherein the control circuitry comprises:

sense circuitry to read the resistive memory cells;

drive circuitry to write the resistive memory cells; and

timing circuitry to control timing applied to at least one of reading and writing the resistive memory cells;

wherein the programmable element is to adjust at least one of:

current applied to the resistive memory cells by the sense circuitry to read the resistive memory cells;

voltage applied to the resistive memory cells by the sense circuitry to read the resistive memory cells;

a logic state threshold to which output of the resistive memory cells is compared;

current applied to the resistive memory cells by the drive circuitry to write the resistive memory cells;

voltage applied to the resistive memory cells by the drive circuitry to write the resistive memory cells;

timing applied to read the resistive memory cells; and timing applied to write the resistive memory cells.

15. The system of claim 13, wherein the control circuitry comprises test circuitry to identify a change in operation of the resistive memory cells, and to change a value stored by the programmable element to compensate for the identified change; wherein the change identified by the test circuitry is due to at least one of temperature dependence and aging.