JP6514567B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP6514567B2 JP6514567B2 JP2015099984A JP2015099984A JP6514567B2 JP 6514567 B2 JP6514567 B2 JP 6514567B2 JP 2015099984 A JP2015099984 A JP 2015099984A JP 2015099984 A JP2015099984 A JP 2015099984A JP 6514567 B2 JP6514567 B2 JP 6514567B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- grooves
- insulating film
- semiconductor device
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 161
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims description 49
- 239000012535 impurity Substances 0.000 claims description 15
- 239000010410 layer Substances 0.000 description 79
- 230000000052 comparative effect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
<半導体装置の構造について>
本実施の形態の半導体装置を、図1〜図4を用いて説明する。図1〜図4は、本実施の形態の半導体装置の断面図である。図2は、図1のA−A線における断面図であり、図3は、図2のC−C線における断面図であり、図4は、図1のB−B線における断面図である。
本実施の形態の半導体装置の製造方法を、図5〜図13を参照して説明する。図1〜図13は、本実施の形態の半導体装置の製造工程中の断面図である。ここでは、nチャネル型の縦型MOSFETを形成する場合について説明する。
以下に、図14および図15を用いて、本実施の形態の半導体装置について説明する。図14および図15は、本実施の形態の半導体装置を示す断面図である。図14は、図2に対応する位置の断面を示し、図15は、図3に対応する位置の断面を示している。つまり、図15は図14のD−D線における断面図である。
EP エピタキシャル層
GD2 下部電極
GE ゲート電極
Claims (12)
- 半導体基板上に形成された半導体層と、
前記半導体基板の上面に沿う第1方向に複数並んで形成され、前記第1方向に直交する第2方向に延在する第1溝と、
複数の前記第1溝のそれぞれの底面において、前記第2方向に複数並んで形成された第2溝と、
前記第1溝および前記第2溝のそれぞれの内側に埋め込まれたゲート電極と、
前記ゲート電極および前記第1溝の間に介在する第1絶縁膜と、
前記ゲート電極および前記第2溝の間に介在する第2絶縁膜と、
前記半導体層の上面に形成されたソース領域と、
前記半導体基板に形成されたドレイン領域と、
を有し、
前記第1方向に隣り合う前記第1溝のそれぞれの前記底面に形成された複数の前記第2溝は、千鳥状に配置されている、半導体装置。 - 半導体基板上に形成された半導体層と、
前記半導体基板の上面に沿う第1方向に複数並んで形成され、前記第1方向に直交する第2方向に延在する第1溝と、
複数の前記第1溝のそれぞれの底面において、前記第2方向に複数並んで形成された第2溝と、
前記第1溝および前記第2溝のそれぞれの内側に埋め込まれたゲート電極と、
前記ゲート電極および前記第1溝の間に介在する第1絶縁膜と、
前記ゲート電極および前記第2溝の間に介在する第2絶縁膜と、
前記半導体層の上面に形成されたソース領域と、
前記半導体基板に形成されたドレイン領域と、
を有し、
前記第1方向に隣り合う前記第1溝のそれぞれの前記底面に形成された複数の前記第2溝は、前記第2方向に所定の周期で並んで配置され、
前記第1方向に隣り合う前記第1溝のうち、一方の前記第1溝の前記底面に形成された複数の前記第2溝は、他方の前記第1溝の前記底面に形成された複数の前記第2溝に対して半周期ずれた位置に配置されている、半導体装置。 - 半導体基板上に形成された半導体層と、
前記半導体基板の上面に沿う第1方向に複数並んで形成され、前記第1方向に直交する第2方向に延在する第1溝と、
複数の前記第1溝のそれぞれの底面において、前記第2方向に複数並んで形成された第2溝と、
前記第1溝および前記第2溝のそれぞれの内側に埋め込まれたゲート電極と、
前記ゲート電極および前記第1溝の間に介在する第1絶縁膜と、
前記ゲート電極および前記第2溝の間に介在する第2絶縁膜と、
前記半導体層の上面に形成されたソース領域と、
前記半導体基板に形成されたドレイン領域と、
を有し、
前記第1方向に隣り合う前記第2溝同士の間の距離は、前記第2方向に隣り合う前記第2溝同士の間の距離よりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記第2方向の前記第2溝の長さは、前記第2方向に隣り合う前記第2溝同士の間の距離よりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記第1方向に隣り合う前記第1溝のうち、一方の前記第1溝の前記底面に形成された前記第2溝の端部と、他方の前記第1溝の前記底面に形成された前記第2溝の端部とは、第2方向において重なる、半導体装置。 - 半導体基板上に形成された半導体層と、
前記半導体基板の上面に沿う第1方向に複数並んで形成され、前記第1方向に直交する第2方向に延在する第1溝と、
複数の前記第1溝のそれぞれの底面において、前記第2方向に複数並んで形成された第2溝と、
前記第1溝および前記第2溝のそれぞれの内側に埋め込まれたゲート電極と、
前記ゲート電極および前記第1溝の間に介在する第1絶縁膜と、
前記ゲート電極および前記第2溝の間に介在する第2絶縁膜と、
前記半導体層の上面に形成されたソース領域と、
前記半導体基板に形成されたドレイン領域と、
を有し、
前記第2絶縁膜の膜厚は、前記第1絶縁膜の膜厚よりも大きい、半導体装置。 - 半導体基板上に形成された半導体層と、
前記半導体基板の上面に沿う第1方向に複数並んで形成され、前記第1方向に直交する第2方向に延在する第1溝と、
複数の前記第1溝のそれぞれの底面において、前記第2方向に複数並んで形成された第2溝と、
前記第1溝および前記第2溝のそれぞれの内側に埋め込まれたゲート電極と、
前記ゲート電極および前記第1溝の間に介在する第1絶縁膜と、
前記ゲート電極および前記第2溝の間に介在する第2絶縁膜と、
前記半導体層の上面に形成されたソース領域と、
前記半導体基板に形成されたドレイン領域と、
を有し、
前記半導体層、前記ソース領域および前記ドレイン領域は第1導電型を有し、
前記第1溝の側壁には、前記第1導電型とは異なる第2導電型の第1半導体領域が形成され、
前記第2方向に並ぶ前記第2溝同士の間の前記第1溝の底面には、前記半導体層よりも濃度が高い前記第1導電型の第2半導体領域が形成された、半導体装置。 - (a)第1導電型の半導体基板を用意する工程、
(b)前記半導体基板の主面上に、前記第1導電型の半導体層を形成する工程、
(c)前記半導体層の上面に、前記半導体基板の上面に沿う第1方向に並ぶ複数の第1溝を形成する工程、
(d)前記第1溝の底面に、前記第1方向に直交する第2方向に並ぶ複数の第2溝を形成する工程、
(e)前記第1溝の側壁を第1絶縁膜で覆い、前記第2溝の側壁および底面を、前記第1絶縁膜よりも膜厚が大きい第2絶縁膜で覆う工程、
(f)前記(e)工程の後、前記第1溝および前記第2溝のそれぞれの内側を覆うゲート電極を形成する工程、
(g)前記第1溝の側壁に、前記第1導電型とは異なる第2導電型の第1半導体領域を形成する工程、
(h)前記半導体層の上面に、前記第1導電型のソース領域を形成する工程、
を有する、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記(d)工程では、前記第1方向に隣り合う前記第1溝のうち、一方の前記第1溝の前記底面に形成する複数の前記第2溝と、他方の前記第1溝の前記底面に形成する複数の前記第2溝とを、千鳥状に配置する、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記第1方向に隣り合う前記第2溝同士の間の距離は、前記第2方向に隣り合う前記第2溝同士の間の距離よりも大きい、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記第1方向に隣り合う前記第1溝のうち、一方の前記第1溝の前記底面に形成された前記第2溝の端部と、他方の前記第1溝の前記底面に形成された前記第2溝の端部とは、第2方向において重なる、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
(c1)前記(c)工程の後、前記(d)工程の前に、前記第1溝の前記底面に前記第1導電型の不純物を導入する工程をさらに有する、半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015099984A JP6514567B2 (ja) | 2015-05-15 | 2015-05-15 | 半導体装置およびその製造方法 |
US15/079,338 US9837492B2 (en) | 2015-05-15 | 2016-03-24 | Semiconductor device and method for manufacturing the same |
US15/797,519 US10170556B2 (en) | 2015-05-15 | 2017-10-30 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015099984A JP6514567B2 (ja) | 2015-05-15 | 2015-05-15 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016219495A JP2016219495A (ja) | 2016-12-22 |
JP6514567B2 true JP6514567B2 (ja) | 2019-05-15 |
Family
ID=57277768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015099984A Active JP6514567B2 (ja) | 2015-05-15 | 2015-05-15 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US9837492B2 (ja) |
JP (1) | JP6514567B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109478567B (zh) * | 2016-07-15 | 2022-12-16 | 罗姆股份有限公司 | 半导体装置 |
EP4009379A1 (en) * | 2020-12-03 | 2022-06-08 | Hitachi Energy Switzerland AG | Power semiconductor device with an insulated trench gate electrode |
EP4210114A1 (en) * | 2022-01-11 | 2023-07-12 | Nexperia B.V. | A metal oxide semiconductor, mosfet, as well as a method of manufacturing such a mosfet |
JP2024031338A (ja) * | 2022-08-26 | 2024-03-07 | ソニーグループ株式会社 | 半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05335582A (ja) * | 1992-05-27 | 1993-12-17 | Omron Corp | 縦型mosfet装置およびその製造方法 |
JP3329707B2 (ja) * | 1997-09-30 | 2002-09-30 | 株式会社東芝 | 半導体装置 |
JP3954541B2 (ja) * | 2003-08-05 | 2007-08-08 | 株式会社東芝 | 半導体装置及びその製造方法 |
GB0403934D0 (en) * | 2004-02-21 | 2004-03-24 | Koninkl Philips Electronics Nv | Trench-gate semiconductor devices and the manufacture thereof |
JP5588121B2 (ja) * | 2009-04-27 | 2014-09-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5013436B2 (ja) * | 2009-06-04 | 2012-08-29 | 三菱電機株式会社 | 電力用半導体装置 |
JP5580150B2 (ja) * | 2010-09-09 | 2014-08-27 | 株式会社東芝 | 半導体装置 |
JP5429365B2 (ja) * | 2011-03-15 | 2014-02-26 | トヨタ自動車株式会社 | 半導体装置 |
US8680607B2 (en) * | 2011-06-20 | 2014-03-25 | Maxpower Semiconductor, Inc. | Trench gated power device with multiple trench width and its fabrication process |
US9024379B2 (en) * | 2012-02-13 | 2015-05-05 | Maxpower Semiconductor Inc. | Trench transistors and methods with low-voltage-drop shunt to body diode |
US8896060B2 (en) * | 2012-06-01 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trench power MOSFET |
JP6061504B2 (ja) * | 2012-06-07 | 2017-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
-
2015
- 2015-05-15 JP JP2015099984A patent/JP6514567B2/ja active Active
-
2016
- 2016-03-24 US US15/079,338 patent/US9837492B2/en active Active
-
2017
- 2017-10-30 US US15/797,519 patent/US10170556B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20160336443A1 (en) | 2016-11-17 |
US10170556B2 (en) | 2019-01-01 |
US9837492B2 (en) | 2017-12-05 |
US20180047811A1 (en) | 2018-02-15 |
JP2016219495A (ja) | 2016-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5849882B2 (ja) | 縦型半導体素子を備えた半導体装置 | |
JP5492610B2 (ja) | 半導体装置及びその製造方法 | |
JP6534813B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5404550B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
CN106992173B (zh) | 包括场效应晶体管的半导体器件 | |
US20130056790A1 (en) | Semiconductor device and method for manufacturing same | |
JP6514567B2 (ja) | 半導体装置およびその製造方法 | |
JP2019519938A (ja) | 短チャネルトレンチ型パワーmosfet | |
JP2018182258A (ja) | 半導体装置及びその製造方法 | |
JP2009081397A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2013201267A (ja) | 半導体装置及びその製造方法 | |
US20190198663A1 (en) | Semiconductor device | |
KR101371495B1 (ko) | 반도체 소자 및 그 제조 방법 | |
JP7079328B2 (ja) | Ldmosデバイスの製造方法 | |
US10811505B2 (en) | Gate electrode having upper and lower capping patterns | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
JP6121350B2 (ja) | 半導体装置及びその製造方法 | |
JP6340200B2 (ja) | 半導体装置およびその製造方法 | |
JP4328797B2 (ja) | 半導体装置 | |
US20180033859A1 (en) | Transistor Device with a Field Electrode that Includes Two Layers | |
JP4735067B2 (ja) | 絶縁ゲート型半導体装置 | |
US20160079350A1 (en) | Semiconductor device and manufacturing method thereof | |
US9647109B2 (en) | Semiconductor device | |
JP5448733B2 (ja) | 半導体装置の製造方法 | |
JP2018174172A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20171115 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180926 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181002 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181130 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190402 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190412 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6514567 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |