JP6449518B2 - 低速バスタイムスタンプの方法及び回路 - Google Patents

低速バスタイムスタンプの方法及び回路 Download PDF

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JP6449518B2
JP6449518B2 JP2018502805A JP2018502805A JP6449518B2 JP 6449518 B2 JP6449518 B2 JP 6449518B2 JP 2018502805 A JP2018502805 A JP 2018502805A JP 2018502805 A JP2018502805 A JP 2018502805A JP 6449518 B2 JP6449518 B2 JP 6449518B2
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clock signal
slave device
time
information
event
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JP2018523236A (ja
JP2018523236A5 (enExample
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ブラッドリー シャープ−ガイスラー
ブラッドリー シャープ−ガイスラー
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Lattice Semiconductor Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
JP2018502805A 2015-07-20 2016-07-18 低速バスタイムスタンプの方法及び回路 Active JP6449518B2 (ja)

Applications Claiming Priority (9)

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US201562194733P 2015-07-20 2015-07-20
US62/194,733 2015-07-20
US201562208041P 2015-08-21 2015-08-21
US62/208,041 2015-08-21
US201562209999P 2015-08-26 2015-08-26
US62/209,999 2015-08-26
US201562217180P 2015-09-11 2015-09-11
US62/217,180 2015-09-11
PCT/US2016/042827 WO2017015222A1 (en) 2015-07-20 2016-07-18 Low-speed bus time stamp methods and circuitry

Related Child Applications (1)

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JP2018227937A Division JP6731996B2 (ja) 2015-07-20 2018-12-05 装置および方法

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JP2018523236A JP2018523236A (ja) 2018-08-16
JP2018523236A5 JP2018523236A5 (enExample) 2018-11-15
JP6449518B2 true JP6449518B2 (ja) 2019-01-09

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JP2018227937A Active JP6731996B2 (ja) 2015-07-20 2018-12-05 装置および方法

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US (2) US10466738B2 (enExample)
EP (2) EP3326073B1 (enExample)
JP (2) JP6449518B2 (enExample)
KR (1) KR101912135B1 (enExample)
CN (2) CN107851081B (enExample)
WO (1) WO2017015222A1 (enExample)

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Publication number Publication date
KR101912135B1 (ko) 2018-10-26
US10884452B2 (en) 2021-01-05
EP3657344B1 (en) 2024-04-10
CN107851081A (zh) 2018-03-27
EP3657344A1 (en) 2020-05-27
KR20180023024A (ko) 2018-03-06
CN112650355B (zh) 2025-07-18
JP2019061709A (ja) 2019-04-18
CN107851081B (zh) 2021-01-15
US20200019209A1 (en) 2020-01-16
US10466738B2 (en) 2019-11-05
CN112650355A (zh) 2021-04-13
WO2017015222A1 (en) 2017-01-26
JP6731996B2 (ja) 2020-07-29
JP2018523236A (ja) 2018-08-16
US20180196465A1 (en) 2018-07-12
EP3326073A4 (en) 2019-03-20
EP3326073B1 (en) 2020-04-08
EP3326073A1 (en) 2018-05-30

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