JP2018523236A5 - - Google Patents

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JP2018523236A5
JP2018523236A5 JP2018502805A JP2018502805A JP2018523236A5 JP 2018523236 A5 JP2018523236 A5 JP 2018523236A5 JP 2018502805 A JP2018502805 A JP 2018502805A JP 2018502805 A JP2018502805 A JP 2018502805A JP 2018523236 A5 JP2018523236 A5 JP 2018523236A5
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Japan
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clock signal
information
slave device
communication link
event
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JP2018502805A
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JP2018523236A (ja
JP6449518B2 (ja
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Priority claimed from PCT/US2016/042827 external-priority patent/WO2017015222A1/en
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JP2018502805A 2015-07-20 2016-07-18 低速バスタイムスタンプの方法及び回路 Active JP6449518B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201562194733P 2015-07-20 2015-07-20
US62/194,733 2015-07-20
US201562208041P 2015-08-21 2015-08-21
US62/208,041 2015-08-21
US201562209999P 2015-08-26 2015-08-26
US62/209,999 2015-08-26
US201562217180P 2015-09-11 2015-09-11
US62/217,180 2015-09-11
PCT/US2016/042827 WO2017015222A1 (en) 2015-07-20 2016-07-18 Low-speed bus time stamp methods and circuitry

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JP2018227937A Division JP6731996B2 (ja) 2015-07-20 2018-12-05 装置および方法

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JP2018523236A JP2018523236A (ja) 2018-08-16
JP2018523236A5 true JP2018523236A5 (enExample) 2018-11-15
JP6449518B2 JP6449518B2 (ja) 2019-01-09

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JP2018227937A Active JP6731996B2 (ja) 2015-07-20 2018-12-05 装置および方法

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US (2) US10466738B2 (enExample)
EP (2) EP3657344B1 (enExample)
JP (2) JP6449518B2 (enExample)
KR (1) KR101912135B1 (enExample)
CN (2) CN107851081B (enExample)
WO (1) WO2017015222A1 (enExample)

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