JP6411480B2 - CCIeプロトコルを介したエラー検出能力 - Google Patents
CCIeプロトコルを介したエラー検出能力 Download PDFInfo
- Publication number
- JP6411480B2 JP6411480B2 JP2016521313A JP2016521313A JP6411480B2 JP 6411480 B2 JP6411480 B2 JP 6411480B2 JP 2016521313 A JP2016521313 A JP 2016521313A JP 2016521313 A JP2016521313 A JP 2016521313A JP 6411480 B2 JP6411480 B2 JP 6411480B2
- Authority
- JP
- Japan
- Prior art keywords
- symbol
- bits
- bit
- bus
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/095—Error detection codes other than CRC and single parity bit codes
- H03M13/096—Checksums
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Information Transfer Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361889030P | 2013-10-09 | 2013-10-09 | |
| US61/889,030 | 2013-10-09 | ||
| US201461946647P | 2014-02-28 | 2014-02-28 | |
| US61/946,647 | 2014-02-28 | ||
| PCT/US2014/059981 WO2015054548A1 (en) | 2013-10-09 | 2014-10-09 | ERROR DETECTION CAPABILITY OVER CCIe PROTOCOL |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016539533A JP2016539533A (ja) | 2016-12-15 |
| JP2016539533A5 JP2016539533A5 (enExample) | 2017-11-02 |
| JP6411480B2 true JP6411480B2 (ja) | 2018-10-24 |
Family
ID=51845514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016521313A Expired - Fee Related JP6411480B2 (ja) | 2013-10-09 | 2014-10-09 | CCIeプロトコルを介したエラー検出能力 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9678828B2 (enExample) |
| EP (1) | EP3055929A1 (enExample) |
| JP (1) | JP6411480B2 (enExample) |
| KR (1) | KR20160070171A (enExample) |
| CN (1) | CN105900340A (enExample) |
| WO (1) | WO2015054548A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9996488B2 (en) | 2013-09-09 | 2018-06-12 | Qualcomm Incorporated | I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator |
| US10353837B2 (en) | 2013-09-09 | 2019-07-16 | Qualcomm Incorporated | Method and apparatus to enable multiple masters to operate in a single master bus architecture |
| US9690725B2 (en) | 2014-01-14 | 2017-06-27 | Qualcomm Incorporated | Camera control interface extension with in-band interrupt |
| US9519603B2 (en) | 2013-09-09 | 2016-12-13 | Qualcomm Incorporated | Method and apparatus to enable multiple masters to operate in a single master bus architecture |
| US9684624B2 (en) | 2014-01-14 | 2017-06-20 | Qualcomm Incorporated | Receive clock calibration for a serial bus |
| US20150234773A1 (en) * | 2014-02-18 | 2015-08-20 | Qualcomm Incorporated | Technique to avoid metastability condition and avoid unintentional state changes of legacy i2c devices on a multi-mode bus |
| US20150248373A1 (en) * | 2014-02-28 | 2015-09-03 | Qualcomm Incorporated | Bit allocation over a shared bus to facilitate an error detection optimization |
| US10089173B2 (en) | 2014-11-26 | 2018-10-02 | Qualcomm Incorporated | Error detection constants of symbol transition clocking transcoding |
| FR3036513B1 (fr) * | 2015-05-19 | 2018-06-08 | Stmicroelectronics (Rousset) Sas | Procede de communication sur un bus bifilaire |
| US9960981B2 (en) | 2015-10-08 | 2018-05-01 | Sony Corporation | Communication device, communication method, program, and communication system |
| JP6976728B2 (ja) * | 2017-06-08 | 2021-12-08 | ソニーセミコンダクタソリューションズ株式会社 | 通信装置、通信方法、プログラム、および、通信システム |
| JP7031961B2 (ja) | 2017-08-04 | 2022-03-08 | ソニーセミコンダクタソリューションズ株式会社 | 通信装置、通信方法、プログラム、および、通信システム |
| JP6953226B2 (ja) * | 2017-08-04 | 2021-10-27 | ソニーセミコンダクタソリューションズ株式会社 | 通信装置、通信方法、プログラム、および、通信システム |
| CN110659238A (zh) * | 2018-06-28 | 2020-01-07 | 鸿富锦精密电子(天津)有限公司 | 数据通信系统 |
| JP7320927B2 (ja) * | 2018-07-02 | 2023-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置及び通信システム |
| CN109861896A (zh) * | 2019-03-29 | 2019-06-07 | 上海剑桥科技股份有限公司 | 高速单总线设备 |
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| US9996488B2 (en) | 2013-09-09 | 2018-06-12 | Qualcomm Incorporated | I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator |
| US10353837B2 (en) | 2013-09-09 | 2019-07-16 | Qualcomm Incorporated | Method and apparatus to enable multiple masters to operate in a single master bus architecture |
| US9690725B2 (en) | 2014-01-14 | 2017-06-27 | Qualcomm Incorporated | Camera control interface extension with in-band interrupt |
| US9519603B2 (en) | 2013-09-09 | 2016-12-13 | Qualcomm Incorporated | Method and apparatus to enable multiple masters to operate in a single master bus architecture |
| WO2015054433A1 (en) | 2013-10-08 | 2015-04-16 | Qualcomm Incorporated | Coexistence of i2c slave devices and camera control interface extension devices on a shared control data bus |
| US9684624B2 (en) | 2014-01-14 | 2017-06-20 | Qualcomm Incorporated | Receive clock calibration for a serial bus |
| US20150248373A1 (en) | 2014-02-28 | 2015-09-03 | Qualcomm Incorporated | Bit allocation over a shared bus to facilitate an error detection optimization |
| US9904637B2 (en) | 2014-11-26 | 2018-02-27 | Qualcomm Incorporated | In-band interrupt time stamp |
-
2014
- 2014-10-09 US US14/511,160 patent/US9678828B2/en not_active Expired - Fee Related
- 2014-10-09 KR KR1020167011504A patent/KR20160070171A/ko not_active Withdrawn
- 2014-10-09 EP EP14792933.5A patent/EP3055929A1/en not_active Withdrawn
- 2014-10-09 WO PCT/US2014/059981 patent/WO2015054548A1/en not_active Ceased
- 2014-10-09 JP JP2016521313A patent/JP6411480B2/ja not_active Expired - Fee Related
- 2014-10-09 CN CN201480055750.7A patent/CN105900340A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN105900340A (zh) | 2016-08-24 |
| WO2015054548A1 (en) | 2015-04-16 |
| JP2016539533A (ja) | 2016-12-15 |
| EP3055929A1 (en) | 2016-08-17 |
| US9678828B2 (en) | 2017-06-13 |
| KR20160070171A (ko) | 2016-06-17 |
| US20150100862A1 (en) | 2015-04-09 |
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