JPS50147204A - - Google Patents
Info
- Publication number
- JPS50147204A JPS50147204A JP5323474A JP5323474A JPS50147204A JP S50147204 A JPS50147204 A JP S50147204A JP 5323474 A JP5323474 A JP 5323474A JP 5323474 A JP5323474 A JP 5323474A JP S50147204 A JPS50147204 A JP S50147204A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Error Detection And Correction (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5323474A JPS50147204A (enExample) | 1974-05-15 | 1974-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5323474A JPS50147204A (enExample) | 1974-05-15 | 1974-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS50147204A true JPS50147204A (enExample) | 1975-11-26 |
Family
ID=12937108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5323474A Pending JPS50147204A (enExample) | 1974-05-15 | 1974-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS50147204A (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6193747A (ja) * | 1984-10-15 | 1986-05-12 | Ascii Corp | 電子装置間のインタフエ−ス装置 |
| JP2016539533A (ja) * | 2013-10-09 | 2016-12-15 | クアルコム，インコーポレイテッド | ＣＣＩｅプロトコルを介したエラー検出能力 |
| US10353837B2 (en) | 2013-09-09 | 2019-07-16 | Qualcomm Incorporated | Method and apparatus to enable multiple masters to operate in a single master bus architecture |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3200374A (en) * | 1962-03-27 | 1965-08-10 | Melpar Inc | Multi-dimension parity check system |
-
1974
- 1974-05-15 JP JP5323474A patent/JPS50147204A/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3200374A (en) * | 1962-03-27 | 1965-08-10 | Melpar Inc | Multi-dimension parity check system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6193747A (ja) * | 1984-10-15 | 1986-05-12 | Ascii Corp | 電子装置間のインタフエ−ス装置 |
| US10353837B2 (en) | 2013-09-09 | 2019-07-16 | Qualcomm Incorporated | Method and apparatus to enable multiple masters to operate in a single master bus architecture |
| JP2016539533A (ja) * | 2013-10-09 | 2016-12-15 | クアルコム，インコーポレイテッド | ＣＣＩｅプロトコルを介したエラー検出能力 |