KR20160070171A - CCIe 프로토콜을 통한 에러 검출 능력 - Google Patents

CCIe 프로토콜을 통한 에러 검출 능력 Download PDF

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Publication number
KR20160070171A
KR20160070171A KR1020167011504A KR20167011504A KR20160070171A KR 20160070171 A KR20160070171 A KR 20160070171A KR 1020167011504 A KR1020167011504 A KR 1020167011504A KR 20167011504 A KR20167011504 A KR 20167011504A KR 20160070171 A KR20160070171 A KR 20160070171A
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South Korea
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bits
bus
symbol
symbols
word
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KR1020167011504A
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English (en)
Korean (ko)
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쇼이치로 센고쿠
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퀄컴 인코포레이티드
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Publication of KR20160070171A publication Critical patent/KR20160070171A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095—Error detection codes other than CRC and single parity bit codes
    • H03M13/096—Checksums

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)
KR1020167011504A 2013-10-09 2014-10-09 CCIe 프로토콜을 통한 에러 검출 능력 Withdrawn KR20160070171A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361889030P 2013-10-09 2013-10-09
US61/889,030 2013-10-09
US201461946647P 2014-02-28 2014-02-28
US61/946,647 2014-02-28
PCT/US2014/059981 WO2015054548A1 (en) 2013-10-09 2014-10-09 ERROR DETECTION CAPABILITY OVER CCIe PROTOCOL

Publications (1)

Publication Number Publication Date
KR20160070171A true KR20160070171A (ko) 2016-06-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167011504A Withdrawn KR20160070171A (ko) 2013-10-09 2014-10-09 CCIe 프로토콜을 통한 에러 검출 능력

Country Status (6)

Country Link
US (1) US9678828B2 (enExample)
EP (1) EP3055929A1 (enExample)
JP (1) JP6411480B2 (enExample)
KR (1) KR20160070171A (enExample)
CN (1) CN105900340A (enExample)
WO (1) WO2015054548A1 (enExample)

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US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
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JP7031961B2 (ja) 2017-08-04 2022-03-08 ソニーセミコンダクタソリューションズ株式会社 通信装置、通信方法、プログラム、および、通信システム
JP6953226B2 (ja) * 2017-08-04 2021-10-27 ソニーセミコンダクタソリューションズ株式会社 通信装置、通信方法、プログラム、および、通信システム
CN110659238A (zh) * 2018-06-28 2020-01-07 鸿富锦精密电子(天津)有限公司 数据通信系统
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Also Published As

Publication number Publication date
JP2016539533A (ja) 2016-12-15
US20150100862A1 (en) 2015-04-09
JP6411480B2 (ja) 2018-10-24
EP3055929A1 (en) 2016-08-17
CN105900340A (zh) 2016-08-24
US9678828B2 (en) 2017-06-13
WO2015054548A1 (en) 2015-04-16

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PA0105 International application

Patent event date: 20160429

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid