JP6366412B2 - パターン形成方法 - Google Patents

パターン形成方法 Download PDF

Info

Publication number
JP6366412B2
JP6366412B2 JP2014158123A JP2014158123A JP6366412B2 JP 6366412 B2 JP6366412 B2 JP 6366412B2 JP 2014158123 A JP2014158123 A JP 2014158123A JP 2014158123 A JP2014158123 A JP 2014158123A JP 6366412 B2 JP6366412 B2 JP 6366412B2
Authority
JP
Japan
Prior art keywords
pattern
line
substrate
opening
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014158123A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016035967A (ja
JP2016035967A5 (https=
Inventor
辻田　好一郎
好一郎 辻田
禎 荒井
禎 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2014158123A priority Critical patent/JP6366412B2/ja
Priority to US14/799,897 priority patent/US9502306B2/en
Publication of JP2016035967A publication Critical patent/JP2016035967A/ja
Publication of JP2016035967A5 publication Critical patent/JP2016035967A5/ja
Application granted granted Critical
Publication of JP6366412B2 publication Critical patent/JP6366412B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
JP2014158123A 2014-08-01 2014-08-01 パターン形成方法 Expired - Fee Related JP6366412B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014158123A JP6366412B2 (ja) 2014-08-01 2014-08-01 パターン形成方法
US14/799,897 US9502306B2 (en) 2014-08-01 2015-07-15 Pattern formation method that includes partially removing line and space pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014158123A JP6366412B2 (ja) 2014-08-01 2014-08-01 パターン形成方法

Publications (3)

Publication Number Publication Date
JP2016035967A JP2016035967A (ja) 2016-03-17
JP2016035967A5 JP2016035967A5 (https=) 2017-09-14
JP6366412B2 true JP6366412B2 (ja) 2018-08-01

Family

ID=55180799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014158123A Expired - Fee Related JP6366412B2 (ja) 2014-08-01 2014-08-01 パターン形成方法

Country Status (2)

Country Link
US (1) US9502306B2 (https=)
JP (1) JP6366412B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412649B1 (en) * 2015-02-13 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device
JP6625200B2 (ja) * 2016-03-24 2019-12-25 東京エレクトロン株式会社 半導体装置の製造方法
JP6966686B2 (ja) 2016-10-21 2021-11-17 株式会社ソシオネクスト 半導体装置
US9741823B1 (en) 2016-10-28 2017-08-22 Internation Business Machines Corporation Fin cut during replacement gate formation
KR102705024B1 (ko) 2016-12-14 2024-09-09 삼성전자주식회사 반도체 장치
US11901190B2 (en) * 2017-11-30 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning
CN110828460B (zh) * 2018-08-14 2022-07-19 中芯国际集成电路制造(北京)有限公司 半导体器件及其形成方法
CN110828466B (zh) * 2019-11-11 2022-03-29 上海华力微电子有限公司 字线制作方法
JP2021153133A (ja) * 2020-03-24 2021-09-30 キオクシア株式会社 パターン形成方法およびテンプレートの製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260705A (ja) * 1999-03-12 2000-09-22 Canon Inc 露光方法ならびにそれを用いたデバイスおよびデバイス製造方法
KR100577610B1 (ko) * 2003-07-15 2006-05-10 삼성전자주식회사 반도체 장치, 반도체 장치의 제조 방법 및 에스램 장치,에스램 장치 제조 방법.
JP2005150494A (ja) * 2003-11-18 2005-06-09 Sony Corp 半導体装置の製造方法
US7759242B2 (en) * 2007-08-22 2010-07-20 Qimonda Ag Method of fabricating an integrated circuit
KR100934836B1 (ko) * 2008-06-19 2009-12-31 주식회사 하이닉스반도체 반도체소자의 미세패턴 형성방법
KR101618749B1 (ko) * 2009-02-27 2016-05-09 삼성전자주식회사 반도체 소자의 패턴 형성 방법
JP4901898B2 (ja) * 2009-03-30 2012-03-21 株式会社東芝 半導体装置の製造方法
JP5499641B2 (ja) * 2009-11-04 2014-05-21 富士通セミコンダクター株式会社 半導体装置及びその設計方法並びに半導体装置の製造方法
JP2011258822A (ja) * 2010-06-10 2011-12-22 Toshiba Corp 半導体装置の製造方法
JP2012033923A (ja) * 2010-07-29 2012-02-16 Nikon Corp 露光方法及び露光装置、並びにデバイス製造方法
US8795953B2 (en) * 2010-09-14 2014-08-05 Nikon Corporation Pattern forming method and method for producing device
CN102683191B (zh) * 2011-03-17 2014-08-27 中芯国际集成电路制造(上海)有限公司 形成栅极图案的方法以及半导体装置
JP5798502B2 (ja) * 2012-01-31 2015-10-21 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US9236267B2 (en) * 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
JP5881567B2 (ja) * 2012-08-29 2016-03-09 株式会社東芝 パターン形成方法
WO2014061760A1 (ja) * 2012-10-19 2014-04-24 株式会社ニコン パターン形成方法及びデバイス製造方法
US9349604B2 (en) * 2013-10-20 2016-05-24 Tokyo Electron Limited Use of topography to direct assembly of block copolymers in grapho-epitaxial applications
US9224617B2 (en) * 2014-01-29 2015-12-29 Globalfoundries Inc. Forming cross-coupled line segments
US9287131B2 (en) * 2014-02-21 2016-03-15 Globalfoundries Inc. Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules

Also Published As

Publication number Publication date
US9502306B2 (en) 2016-11-22
JP2016035967A (ja) 2016-03-17
US20160035628A1 (en) 2016-02-04

Similar Documents

Publication Publication Date Title
JP6366412B2 (ja) パターン形成方法
US7537866B2 (en) Patterning a single integrated circuit layer using multiple masks and multiple masking layers
CN101419906B (zh) 半导体器件微图案的形成方法
TWI473143B (zh) 在半導體裝置中形成微型圖案之方法
KR20140041344A (ko) 패턴 형성 방법
US9006911B2 (en) Method for forming patterns of dense conductor lines and their contact pads, and memory array having dense conductor lines and contact pads
KR20140016664A (ko) 더미 패턴들이 잔류하지 않는 미세 패턴 형성 방법 및 포토 마스크 시스템
US9559015B2 (en) Method of forming a conductive line pattern in FinFET semiconductor devices
US7820345B2 (en) Exposure mask and a method of making a semiconductor device using the mask
US10535646B2 (en) Systems and methods for a sequential spacer scheme
JP2007150166A (ja) 半導体装置の製造方法
KR20150094073A (ko) 더블 패터닝을 이용한 반도체 소자 형성 방법
US8080349B2 (en) Exposure mask and method for manufacturing semiconductor device using the same
CN110707005B (zh) 半导体装置及其形成方法
CN104934302B (zh) 半导体器件的制作方法
EP3499310A1 (en) A method for producing a pattern of features by lithography and etching
KR20130049510A (ko) 반도체 소자의 제조 방법
US10170309B2 (en) Dummy pattern addition to improve CD uniformity
US8512938B2 (en) Methods of forming a pattern in a material and methods of forming openings in a material to be patterned
US6767672B2 (en) Method for forming a phase-shifting mask for semiconductor device manufacture
KR100899397B1 (ko) 스페이서 패터닝 기술을 이용한 미세 패턴 형성 방법
JP2007123342A (ja) 半導体装置の製造方法。
CN107464744A (zh) 半导体结构及其制造方法
US9436081B2 (en) Methods of modifying masking reticles to remove forbidden pitch regions thereof
US8057987B2 (en) Patterning method of semiconductor device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170801

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170801

TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180530

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180604

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180703

R151 Written notification of patent or utility model registration

Ref document number: 6366412

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees