JP6283218B2 - 基板の反り矯正装置及び基板の反り矯正方法 - Google Patents

基板の反り矯正装置及び基板の反り矯正方法 Download PDF

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Publication number
JP6283218B2
JP6283218B2 JP2013264875A JP2013264875A JP6283218B2 JP 6283218 B2 JP6283218 B2 JP 6283218B2 JP 2013264875 A JP2013264875 A JP 2013264875A JP 2013264875 A JP2013264875 A JP 2013264875A JP 6283218 B2 JP6283218 B2 JP 6283218B2
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Japan
Prior art keywords
substrate
disposed
warpage
spacer
gas supply
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JP2013264875A
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English (en)
Japanese (ja)
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JP2014195042A (ja
JP2014195042A5 (https=
Inventor
冬竜 萬年
冬竜 萬年
聡 上條
聡 上條
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2013264875A priority Critical patent/JP6283218B2/ja
Priority to US14/178,664 priority patent/US9362151B2/en
Publication of JP2014195042A publication Critical patent/JP2014195042A/ja
Publication of JP2014195042A5 publication Critical patent/JP2014195042A5/ja
Application granted granted Critical
Publication of JP6283218B2 publication Critical patent/JP6283218B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0616—Monitoring of warpages, curvatures, damages, defects or the like
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7611—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2013264875A 2013-02-27 2013-12-24 基板の反り矯正装置及び基板の反り矯正方法 Active JP6283218B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013264875A JP6283218B2 (ja) 2013-02-27 2013-12-24 基板の反り矯正装置及び基板の反り矯正方法
US14/178,664 US9362151B2 (en) 2013-02-27 2014-02-12 Substrate warp correcting device and substrate warp correcting method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013036842 2013-02-27
JP2013036842 2013-02-27
JP2013264875A JP6283218B2 (ja) 2013-02-27 2013-12-24 基板の反り矯正装置及び基板の反り矯正方法

Publications (3)

Publication Number Publication Date
JP2014195042A JP2014195042A (ja) 2014-10-09
JP2014195042A5 JP2014195042A5 (https=) 2016-10-20
JP6283218B2 true JP6283218B2 (ja) 2018-02-21

Family

ID=51388547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013264875A Active JP6283218B2 (ja) 2013-02-27 2013-12-24 基板の反り矯正装置及び基板の反り矯正方法

Country Status (2)

Country Link
US (1) US9362151B2 (https=)
JP (1) JP6283218B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102393166B1 (ko) * 2020-11-23 2022-05-02 주식회사 알에스이 인쇄회로기판 휨 교정 기구

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015019035A (ja) * 2013-06-11 2015-01-29 イビデン株式会社 配線板の製造方法、配線板の反り修正方法及び配線板の製造装置
US9633874B1 (en) * 2014-07-17 2017-04-25 Altera Corporation Package substrate warpage reshaping apparatus and method
BR112015020761A2 (pt) 2014-09-27 2017-07-18 Intel Corp controle de empenamento de substrato com o uso de vidro temperado com aquecimento unidirecional
US10325790B2 (en) * 2016-04-29 2019-06-18 Applied Materials, Inc. Methods and apparatus for correcting substrate deformity
US20180177045A1 (en) * 2016-12-21 2018-06-21 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding Component in Component Carrier by Component Fixation Structure
KR101842590B1 (ko) * 2017-11-23 2018-03-29 주식회사 다이나테크 패널 타입 몰드 웨이퍼의 휨 교정장치

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553484A (en) * 1978-10-16 1980-04-18 Fujitsu Ltd Method of correcting slet of printed board
JPH02116550A (ja) * 1988-10-26 1990-05-01 Matsushita Electric Works Ltd プリント配線板の反り矯正方法
JPH09148729A (ja) * 1995-11-28 1997-06-06 Nec Kansai Ltd はんだリフロー装置及びプリント基板製造方法
JP2011222578A (ja) * 2010-04-05 2011-11-04 Murata Mfg Co Ltd 電子部品製造装置及び電子部品製造方法
KR20120009713A (ko) * 2010-07-20 2012-02-02 삼성전자주식회사 인쇄회로기판 조립체의 제조장치 및 이의 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102393166B1 (ko) * 2020-11-23 2022-05-02 주식회사 알에스이 인쇄회로기판 휨 교정 기구

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Publication number Publication date
JP2014195042A (ja) 2014-10-09
US20140242729A1 (en) 2014-08-28
US9362151B2 (en) 2016-06-07

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