JP6273322B2 - Soi基板の製造方法 - Google Patents
Soi基板の製造方法 Download PDFInfo
- Publication number
- JP6273322B2 JP6273322B2 JP2016139399A JP2016139399A JP6273322B2 JP 6273322 B2 JP6273322 B2 JP 6273322B2 JP 2016139399 A JP2016139399 A JP 2016139399A JP 2016139399 A JP2016139399 A JP 2016139399A JP 6273322 B2 JP6273322 B2 JP 6273322B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- insulating layer
- deuterium
- semiconductor substrate
- soi substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 36
- 229910052805 deuterium Inorganic materials 0.000 claims description 29
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000010884 ion-beam technique Methods 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 239000001257 hydrogen Substances 0.000 claims description 10
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000001816 cooling Methods 0.000 claims description 2
- 238000009736 wetting Methods 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- -1 hydrogen ions Chemical class 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 125000004431 deuterium atom Chemical group 0.000 description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000005685 electric field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Description
本方法は、第1半導体基板を用意し、第1ウェハを形成するために第1半導体基板の上面で第1絶縁層を成長させ、第1絶縁層の上面から既定の深さまでドープ層を形成するために第1半導体基板にイオンビームを照射し、第2半導体基板を用意し、第2ウェハを形成するために第2半導体基板の上面で第2絶縁層を成長させ、第1ウェハを第2ウェハに接合し、第1ウェハ及び第2ウェハを重水素雰囲気中でアニールし、第1ウェハの一部を第2ウェハから分離し、重水素ドープ層を第2ウェハ上に形成することを含む。
ステップ101(S101):第1半導体基板を用意する。
ステップ102(S102):第1ウェハを形成するために第1半導体基板の上面に第1絶縁層を形成する。
ステップS103(S103):水素をソースガスとして使用し、第1絶縁層の上面から既定の深さまでドープ層を形成するために、第1半導体基板に水素イオンビームを照射する。
ステップ104(S104):第2半導体基板を用意する。
ステップ105(S105):第2ウェハを形成するために第2半導体基板の上面に第2絶縁層を形成する。
ステップ106(S106):第1ウェハを第2ウェハに向い合わせで接合する。
ステップ107(S107):第1ウェハ及び第2ウェハを重水素雰囲気中でアニールする。
ステップ108(S108):第1ウェハの一部を第2ウェハから分離する。
ステップ109(S109):重水素ドープ層を第2ウェハ上に形成する。
ステップ110(S110):第1ウェハの分離部を再使用する。
次のステップについて図2Dを参照する。第2半導体基板200を用意し、第2半導体基板200の材料はIV族、SiGe、III−V族化合物、III族−窒素化合物又はII−VI族化合物になり得る。一実施形態において、第2半導体基板200の材料は単結晶シリコンである。
親水性接合法の詳細なステップにはさらに、第1絶縁層104及び第2絶縁層204を湿潤させるステップと、湿潤した第1絶縁層104を湿潤した第2絶縁層204と接触させるステップと、第1絶縁層104を第2絶縁層204に緊密に接合するために第1絶縁層104及び第2絶縁層204に加圧するステップとが含まれる。
本発明は、半導体デバイス製造用のSOI基板を提供する。このSOI基板は、半導体デバイスのドレインとソースとの間の寄生容量を低下させることができ、SOI基板にドープされた重水素原子(又は重水素イオン)は、SOI基板上でのゲート酸化物の成長後、ゲート酸化物とSOI基板との間の界面へと拡散し得て、重水素原子(又は重水素イオン)は半導体原子に共有結合してダングリングボンドを排除し且つホットキャリア効果に対する半導体デバイスのレジリエンスを上昇させる。さらに、このSOI基板の製造方法は極めて高い重水素圧力を必要とせず、SOI基板の製造コストを大幅に削減できる。
Claims (9)
- 第1半導体基板を用意するステップと、
第1ウェハを形成するために前記第1半導体基板の上面に第1絶縁層を形成するステップと、
前記第1絶縁層の上面から既定の深さまで水素ドープ層を形成するために前記第1半導体基板に水素イオンビームを照射するステップと、
第2半導体基板を用意するステップと、
第2ウェハを形成するために前記第2半導体基板の上面で第2絶縁層を成長させるステップと、
前記第1ウェハを前記第2ウェハに向い合わせで接合するステップと、
前記第1ウェハ及び前記第2ウェハを重水素雰囲気中でアニールして、前記水素ドープ層を複数の重水素ドープバブルに変化させるステップと、
前記第1絶縁層を介して重水素ドープ層を前記第2ウェハ上に形成するために、前記第1ウェハの一部を前記第2ウェハから分離するステップであって、前記複数の重水素ドープバブルが前記重水素ドープ層内にあるステップと、を含む、
SOI基板の製造方法。 - 前記水素イオンビームの加速電圧は1〜200kevであり、前記水素イオンビームのドープ量は1016イオン/cm2〜2x1017イオン/cm2であることを特徴とする、請求項1に記載の方法。
- 前記第1ウェハを前記第2ウェハに向い合わせで200〜400℃で接合することを特徴とする、請求項1に記載の方法。
- 前記第1ウェハを第2ウェハに接合するステップはさらに、前記第1絶縁層及び前記第2絶縁層を湿潤させ、前記第1絶縁層を前記第2絶縁層と接触させ、前記第1絶縁層を前記第2絶縁層上に接合するために前記第1絶縁層及び前記第2絶縁層に加圧することを含むことを特徴とする、請求項1に記載の方法。
- 前記重水素雰囲気の圧力は10〜1000トールであることを特徴とする、請求項1に記載の方法。
- 前記重水素ドープ層の重水素濃度の平均値の範囲は1010原子/cm3〜8x1018原子/cm3であることを特徴とする、請求項1に記載の方法。
- 前記第1ウェハ及び前記第2ウェハをアニールするステップはさらに、前記第1ウェハ及び前記第2ウェハを600〜1200℃まで加熱し、前記第1ウェハ及び前記第2ウェハを400〜600℃まで冷却することを含むことを特徴とする、請求項1に記載の方法。
- 前記第1ウェハの一部を前記第2ウェハから分離した後に、前記第2ウェハを600〜1200℃まで再度加熱するステップをさらに含むことを特徴とする、請求項1に記載の方法。
- 前記第1ウェハ及び前記第2ウェハを再度加熱する時間は30分〜8時間であることを特徴とする、請求項8に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610120843.4 | 2016-03-03 | ||
CN201610120843.4A CN107154379B (zh) | 2016-03-03 | 2016-03-03 | 绝缘层上顶层硅衬底及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017157811A JP2017157811A (ja) | 2017-09-07 |
JP6273322B2 true JP6273322B2 (ja) | 2018-01-31 |
Family
ID=59650631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016139399A Active JP6273322B2 (ja) | 2016-03-03 | 2016-07-14 | Soi基板の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10170356B2 (ja) |
JP (1) | JP6273322B2 (ja) |
KR (1) | KR101869641B1 (ja) |
CN (1) | CN107154379B (ja) |
DE (1) | DE102016119644B4 (ja) |
TW (1) | TWI611462B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107154379B (zh) | 2016-03-03 | 2020-01-24 | 上海新昇半导体科技有限公司 | 绝缘层上顶层硅衬底及其制造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US5872387A (en) | 1996-01-16 | 1999-02-16 | The Board Of Trustees Of The University Of Illinois | Deuterium-treated semiconductor devices |
US6548382B1 (en) * | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
JPH11330438A (ja) | 1998-05-08 | 1999-11-30 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US6995075B1 (en) * | 2002-07-12 | 2006-02-07 | Silicon Wafer Technologies | Process for forming a fragile layer inside of a single crystalline substrate |
US6992025B2 (en) * | 2004-01-12 | 2006-01-31 | Sharp Laboratories Of America, Inc. | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation |
US20060094259A1 (en) * | 2004-11-03 | 2006-05-04 | Freescale Semiconductor, Inc. | Forming gas anneal process for high dielectric constant gate dielectrics in a semiconductor fabrication process |
US7148124B1 (en) * | 2004-11-18 | 2006-12-12 | Alexander Yuri Usenko | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers |
DE102004060363B4 (de) | 2004-12-15 | 2010-12-16 | Austriamicrosystems Ag | Halbleitersubstrat mit pn-Übergang und Verfahren zur Herstellung |
US20060270192A1 (en) * | 2005-05-24 | 2006-11-30 | International Business Machines Corporation | Semiconductor substrate and device with deuterated buried layer |
JP2007141946A (ja) * | 2005-11-15 | 2007-06-07 | Sumco Corp | Soi基板の製造方法及びこの方法により製造されたsoi基板 |
US7378335B2 (en) * | 2005-11-29 | 2008-05-27 | Varian Semiconductor Equipment Associates, Inc. | Plasma implantation of deuterium for passivation of semiconductor-device interfaces |
US7608521B2 (en) * | 2006-05-31 | 2009-10-27 | Corning Incorporated | Producing SOI structure using high-purity ion shower |
EP1993128A3 (en) * | 2007-05-17 | 2010-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
EP1993127B1 (en) | 2007-05-18 | 2013-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate |
US7781306B2 (en) * | 2007-06-20 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor substrate and method for manufacturing the same |
EP2045844A1 (en) * | 2007-10-03 | 2009-04-08 | ABB Technology AG | Semiconductor Module |
US7989305B2 (en) * | 2007-10-10 | 2011-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate using cluster ion |
JP6056516B2 (ja) * | 2013-02-01 | 2017-01-11 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
CN107154379B (zh) | 2016-03-03 | 2020-01-24 | 上海新昇半导体科技有限公司 | 绝缘层上顶层硅衬底及其制造方法 |
-
2016
- 2016-03-03 CN CN201610120843.4A patent/CN107154379B/zh active Active
- 2016-06-15 TW TW105118826A patent/TWI611462B/zh active
- 2016-06-30 US US15/198,805 patent/US10170356B2/en active Active
- 2016-07-14 JP JP2016139399A patent/JP6273322B2/ja active Active
- 2016-10-14 DE DE102016119644.4A patent/DE102016119644B4/de active Active
-
2017
- 2017-02-21 KR KR1020170023070A patent/KR101869641B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US20170256438A1 (en) | 2017-09-07 |
CN107154379A (zh) | 2017-09-12 |
TWI611462B (zh) | 2018-01-11 |
DE102016119644A1 (de) | 2017-09-07 |
DE102016119644B4 (de) | 2023-02-02 |
KR101869641B1 (ko) | 2018-06-20 |
TW201732886A (zh) | 2017-09-16 |
US10170356B2 (en) | 2019-01-01 |
KR20170103648A (ko) | 2017-09-13 |
CN107154379B (zh) | 2020-01-24 |
JP2017157811A (ja) | 2017-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100755368B1 (ko) | 3차원 구조를 갖는 반도체 소자의 제조 방법들 및 그에의해 제조된 반도체 소자들 | |
JP2009164643A (ja) | ナノsoiウェーハの製造方法 | |
WO2015136834A1 (ja) | 貼り合わせsoiウェーハの製造方法 | |
WO2007125771A1 (ja) | Soiウエーハの製造方法 | |
JP5194508B2 (ja) | Soiウエーハの製造方法 | |
JP6174756B2 (ja) | Soi基板の製造方法 | |
JP5292810B2 (ja) | Soi基板の製造方法 | |
US10014210B2 (en) | SOI substrate and manufacturing method thereof | |
JP5320954B2 (ja) | Soiウェーハの製造方法 | |
JP6273322B2 (ja) | Soi基板の製造方法 | |
CN110400773B (zh) | 一种采用快速热处理工艺制备soi硅片的方法 | |
JP2000196047A (ja) | Soi基板及びその製造方法 | |
CN107154347B (zh) | 绝缘层上顶层硅衬底及其制造方法 | |
JP2022077203A (ja) | 貼り合わせウェーハ及び貼り合わせウェーハの製造方法 | |
RU2497231C1 (ru) | Способ изготовления структуры кремний-на-изоляторе | |
JP5096780B2 (ja) | Soiウエーハの製造方法 | |
JP5572914B2 (ja) | 直接接合ウェーハの製造方法 | |
WO2022179615A1 (zh) | 绝缘体上半导体结构的制造方法 | |
TW202309355A (zh) | 製造絕緣體上矽晶片的方法 | |
JP2008205218A (ja) | 半導体基板 | |
JP2013251340A (ja) | 複合基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170808 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20171012 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20171219 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180105 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6273322 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |