JP6271356B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 description 239
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 230
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- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
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- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
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- 239000011229 interlayer Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
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- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 2
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- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Description
本実施形態の半導体装置は、対向する第1の面と第2の面を有するSiC基板と、SiC基板の第1の面側に設けられ、DLTS(Deep Level Transient Specroscopy)により測定されるZ1/2準位密度が1×1011cm−3以下の低準位密度領域を有する第1導電型のSiC層と、SiC層の表面に設けられた第2導電型のSiC領域と、SiC領域上に設けられた第1の電極と、SiC基板の第2の面側に設けられた第2の電極と、を備える。
本実施形態の半導体装置は、対向する第1の面と第2の面を有する第1導電型のSiC基板と、SiC基板の第1の面側に設けられた第1導電型のSiC層と、SiC層の表面に設けられ、DLTS(Deep Level Transient Specroscopy)により測定されるZ1/2準位密度が1×1011cm−3以下の低準位密度領域を有する第2導電型の第1のSiC領域と、第1のSiC領域の表面に設けられた第1導電型の第2のSiC領域と、SiC層、第1のSiC領域の表面に連続的に設けられたゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極と、第2のSiC領域上に設けられた第1の電極と、SiC基板の第2の面側に設けられた第2の電極と、を備える。
本実施形態の半導体装置は、対向する第1の面と第2の面を有する第2導電型のSiC基板と、SiC基板の第1の面側に設けられた第1導電型のSiC層と、SiC層の表面に設けられ、DLTSにより測定されるZ1/2準位密度が1×1011cm−3以下の低準位密度領域を有する第2導電型の第1のSiC領域と、第1のSiC領域の表面に設けられた第1導電型の第2のSiC領域と、SiC層、第1のSiC領域の表面に連続的に形成されたゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極と、第2のSiC領域上に設けられた第1の電極と、SiC基板の第2の面側に設けられた第2の電極と、を備える。
11 低準位密度領域
12 SiC層(ドリフト層)
14 SiC領域(アノード領域)
16 第1の電極(アノード電極)
18 第2の電極(カソード電極)
26 第1のSiC領域(pウェル領域)
28 第2のSiC領域(ソース領域)
38 ゲート絶縁膜
40 ゲート電極
34 第1の電極(ソース・pウェル共通電極)
44 第2の電極(ドレイン電極)
60 SiC基板
66 第1のSiC領域(エミッタ領域)
68 第2のSiC領域(コレクタ領域)
74 第1の電極(エミッタ・pベース共通電極)
84 第2の電極(コレクタ電極)
100 PINダイオード(半導体装置)
200 MOSFET(半導体装置)
300 IGBT(半導体装置)
Claims (9)
- SiC層に、p型不純物、n型不純物またはC(炭素)をイオン注入し、その後、
前記SiC層を第1のアニールを行い、その後、
C(炭素)を含有するガスが存在する雰囲気中で、前記第1のアニールよりも低温で、前記SiC層を第2のアニールまたは酸化を行い、
前記第2のアニールは膜の成長を伴わない、
半導体装置の製造方法。 - 前記第2のアニールまたは酸化の温度は、1000度以上1600度未満である請求項1記載の半導体装置の製造方法。
- 前記C(炭素)を含有するガスは、炭化水素のガスである請求項1または請求項2記載の半導体装置の製造方法。
- 前記第1のアニールの温度は、1600度以上1800度以下である請求項1ないし請求項3いずれか一項記載の半導体装置の製造方法。
- 前記炭化水素は、メタン、プロパン、または、アセチレンである請求項3記載の半導体装置の製造方法。
- 前記イオン注入のドーズ量は、1×1015cm−2以上である請求項1ないし請求項5いずれか一項記載の半導体装置の製造方法。
- 前記第2のアニールまたは酸化の前にSiC基板上に、前記SiC層をエピタキシャル成長法により形成する請求項1ないし請求項6いずれか一項記載の半導体装置の製造方法。
- 前記イオン注入の際に、前記n型不純物または前記p型不純物を、前記SiC層に選択的にイオン注入する請求項1ないし請求項7いずれか一項記載の半導体装置の製造方法。
- 前記第2のアニールまたは酸化の温度は1400度以上である請求項2記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014140042A JP6271356B2 (ja) | 2014-07-07 | 2014-07-07 | 半導体装置の製造方法 |
US14/690,968 US9786513B2 (en) | 2014-07-07 | 2015-04-20 | Manufacturing method for semiconductor device including first and second thermal treatments |
US15/674,038 US10177009B2 (en) | 2014-07-07 | 2017-08-10 | Manufacturing method for semiconductor device including first and second thermal treatments |
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JP2014146748A (ja) * | 2013-01-30 | 2014-08-14 | Toshiba Corp | 半導体装置及びその製造方法並びに半導体基板 |
DE112015000206T5 (de) * | 2014-10-03 | 2016-08-25 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
JP6415946B2 (ja) | 2014-11-26 | 2018-10-31 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
WO2017090285A1 (ja) * | 2015-11-24 | 2017-06-01 | 住友電気工業株式会社 | 炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法 |
JP6061017B1 (ja) * | 2015-12-17 | 2017-01-18 | 株式会社Sumco | 半導体エピタキシャルウェーハの汚染評価方法およびそれを用いたエピタキシャル成長装置の汚染評価方法 |
JP6911453B2 (ja) * | 2017-03-28 | 2021-07-28 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP6862381B2 (ja) | 2018-03-02 | 2021-04-21 | 株式会社東芝 | 半導体装置 |
IT201800007263A1 (it) * | 2018-07-17 | 2020-01-17 | Sensore ottico a bassa potenza per applicazioni di consumo, industriali e automobilistiche | |
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JP2021034726A (ja) * | 2019-08-13 | 2021-03-01 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP7326227B2 (ja) | 2020-07-01 | 2023-08-15 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機 |
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