JP6265175B2 - 半導体素子の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 278
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 238000003825 pressing Methods 0.000 claims description 106
- 239000000758 substrate Substances 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 27
- 239000000853 adhesive Substances 0.000 claims description 20
- 230000001070 adhesive effect Effects 0.000 claims description 20
- 238000003776 cleavage reaction Methods 0.000 claims description 16
- 230000007017 scission Effects 0.000 claims description 16
- 239000013078 crystal Substances 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 136
- 230000001681 protective effect Effects 0.000 description 17
- 239000000463 material Substances 0.000 description 6
- 238000000605 extraction Methods 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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Description
る。
<実施形態1に係る発光素子の製造方法>
(半導体ウエハの準備工程)
(割断起点部22の形成工程)
(発光素子を割断する工程)
(押圧部材30)
(粘着シート50)
(受け皿40)
(保護シート52)
(押圧部材30の走査パターンSP)
(発光素子の取り出し工程)
<実施形態2>
5…基板
5a…第一主面
5b…第二主面
6…第1半導体層
7…第2半導体層
8…活性層
10…発光素子
11…半導体構造
13…透光性導電層
14…保護膜
18…光取り出し面
20…半導体ウエハ
22…割断起点部
30…押圧部材
31…先端部
33…走査制御部
40…受け皿
42…フレーム
50…粘着シート
52…保護シート
LB…レーザ光
OL…オリエンテーションフラット面
BS…半導体ウエハ(基板)の裏面
SP、SP’…走査パターン
Claims (11)
- 基板上に半導体構造が設けられた半導体ウエハを準備する工程と、
前記半導体ウエハに、平面視形状が五角形以上の多角形である複数の半導体素子に分割するための割断起点部を形成する工程と、
押圧部材を前記半導体ウエハに押し当てた状態で、前記半導体ウエハ上を移動させ、前記半導体ウエハを前記割断起点部より切り離して個別の半導体素子に分割する工程と、
を含み、
前記押圧部材は、前記半導体ウエハに押し当てる先端部が曲面であり、
前記割断起点部は、前記半導体ウエハの前記押圧部材が押し当てられる被押圧面に達しており、
前記被押圧面は、前記基板の半導体構造が形成された面とは反対側の面であり、
前記割断起点部は、前記基板の内部にレーザ光を集光させて形成され、
前記半導体素子に分割する工程において、前記押圧部材を、前記半導体ウエハの平面視において、前記半導体素子の外形の多角形を構成するいずれの辺とも平行でない方向に走査してなる半導体素子の製造方法。 - 基板上に半導体構造が設けられた半導体ウエハを準備する工程と、
前記半導体ウエハに、平面視形状が五角形以上の多角形である複数の半導体素子に分割するための割断起点部を形成する工程と、
押圧部材を前記半導体ウエハに押し当てた状態で、前記半導体ウエハ上を移動させ、前記半導体ウエハを前記割断起点部より切り離して個別の半導体素子に分割する工程と、
を含み、
前記押圧部材は、前記半導体ウエハに押し当てる先端部が曲面であり、
前記割断起点部は、前記半導体ウエハの前記押圧部材が押し当てられる被押圧面に達しており、
前記被押圧面は、前記基板の半導体構造が形成された面とは反対側の面であり、
前記割断起点部は、前記基板の内部にレーザ光を集光させて形成され、
前記半導体素子に分割する工程において、前記押圧部材を、前記半導体ウエハの平面視において、該半導体ウエハのオリエンテーションフラット面に対して傾斜した方向に走査してなる半導体素子の製造方法。 - 基板上に半導体構造が設けられた半導体ウエハを準備する工程と、
前記半導体ウエハに、平面視形状が五角形以上の多角形である複数の半導体素子に分割するための割断起点部を形成する工程と、
押圧部材を前記半導体ウエハに押し当てた状態で、前記半導体ウエハ上を移動させ、前記半導体ウエハを前記割断起点部より切り離して個別の半導体素子に分割する工程と、
を含み、
前記押圧部材は、前記半導体ウエハに押し当てる先端部が曲面であり、
前記割断起点部は、前記半導体ウエハの前記押圧部材が押し当てられる被押圧面に達しており、
前記被押圧面は、前記基板の半導体構造が形成された面とは反対側の面であり、
前記割断起点部は、前記基板の内部にレーザ光を集光させて形成され、
前記押圧部材の先端部が球面である半導体素子の製造方法。 - 請求項3に記載の半導体素子の製造方法であって、
前記先端部の外形は、前記半導体素子の平面視形状の外接円の直径よりも長い半導体素子の製造方法。 - 請求項4に記載の半導体素子の製造方法であって、
前記先端部の外形は、前記半導体素子の平面視形状の外接円の直径の2倍以上である半導体素子の製造方法。 - 基板上に半導体構造が設けられた半導体ウエハを準備する工程と、
前記半導体ウエハに、平面視形状が五角形以上の多角形である複数の半導体素子に分割するための割断起点部を形成する工程と、
押圧部材を前記半導体ウエハに押し当てた状態で、前記半導体ウエハ上を移動させ、前記半導体ウエハを前記割断起点部より切り離して個別の半導体素子に分割する工程と、
を含み、
前記押圧部材は、前記半導体ウエハに押し当てる先端部が曲面であり、
前記割断起点部は、前記半導体ウエハの前記押圧部材が押し当てられる被押圧面に達しており、
前記被押圧面は、前記基板の半導体構造が形成された面とは反対側の面であり、
前記割断起点部は、前記基板の内部にレーザ光を集光させて形成され、
前記押圧部材の先端部を球面状に形成してなる半導体素子の製造方法。 - 請求項1〜6のいずれか一項に記載の半導体素子の製造方法であって、
前記割断起点部は、前記基板の前記半導体構造の近傍にまで形成される半導体素子の製造方法。 - 請求項1〜7のいずれか一項に記載の半導体素子の製造方法であって、
前記半導体素子に分割する工程において、前記半導体ウエハは、前記押圧部材が押し当てられる被押圧面とは反対側の面が粘着シートに固定される半導体素子の製造方法。 - 請求項8に記載の半導体素子の製造方法であって、
前記被押圧面側に保護シートを設け、前記押圧部材が保護シートを介して前記半導体ウエハを押圧することで半導体素子に分割する半導体素子の製造方法。 - 請求項1〜9のいずれか一項に記載の半導体素子の製造方法であって、
前記割断起点部が平面視において屈曲した折れ線状に形成されてなる半導体素子の製造方法。 - 請求項1〜10のいずれか一項に記載の半導体素子の製造方法であって、
前記基板は六方晶系の結晶構造を有し、
前記半導体素子の平面視形状は六角形である半導体素子の製造方法。
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JP2015131776A JP6265175B2 (ja) | 2015-06-30 | 2015-06-30 | 半導体素子の製造方法 |
US15/196,787 US10115857B2 (en) | 2015-06-30 | 2016-06-29 | Method for manufacturing semiconductor element of polygon shape |
US16/149,898 US10388827B2 (en) | 2015-06-30 | 2018-10-02 | Method for manufacturing semiconductor element by dividing semiconductor wafer using pressing member having tip portion |
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JP7214306B2 (ja) * | 2018-04-27 | 2023-01-30 | 株式会社ディスコ | 被加工物の加工方法 |
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JP7339509B2 (ja) * | 2019-08-02 | 2023-09-06 | 日亜化学工業株式会社 | 発光素子の製造方法 |
EP3772748A1 (en) * | 2019-08-07 | 2021-02-10 | Nichia Corporation | Method of manufacturing light emitting element |
JP6982264B2 (ja) * | 2019-08-07 | 2021-12-17 | 日亜化学工業株式会社 | 発光素子の製造方法 |
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US10115857B2 (en) | 2018-10-30 |
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