JP6245266B2 - 半導体アキシャルパッケージ - Google Patents
半導体アキシャルパッケージ Download PDFInfo
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- JP6245266B2 JP6245266B2 JP2015541755A JP2015541755A JP6245266B2 JP 6245266 B2 JP6245266 B2 JP 6245266B2 JP 2015541755 A JP2015541755 A JP 2015541755A JP 2015541755 A JP2015541755 A JP 2015541755A JP 6245266 B2 JP6245266 B2 JP 6245266B2
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- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000000034 method Methods 0.000 claims description 38
- 229910000679 solder Inorganic materials 0.000 claims description 30
- 239000005022 packaging material Substances 0.000 claims description 13
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 3
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- 230000008569 process Effects 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/83801—Soldering or alloying
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims (25)
- 軸方向に取り付け可能な素子であって、
(a)下部および上部電気接点を備える半導体チップと、
(b)電気的および機械的に前記半導体チップの前記下部電気接点に接続する下部ダイパッドと、
(c)電気的および機械的に前記半導体チップの前記上部電気接点に接続する上部ダイパッドと、
(d)第1の軸方向に延在する電気リードであって、電気的および機械的に前記上部ダイパッドに接続し、第1の軸方向に延在する電気リードと、
(d)第2の軸方向に延在する電気リードであって、電気的および機械的に前記下部ダイパッドに接続し、前記第1の軸方向とは反対の第2の軸方向に延在する電気リードと、
(e)前記半導体チップ、前記上部および下部ダイパッド、および前記第1および第2の軸方向に延在する電気リードの一部を封止するパッケージング素材と、
を備え、
前記第1および第2の軸方向に延在する電気リードは、共通の平面に延在し、
前記第1および第2の軸方向に延在する電気リードは前記パッケージング素材から延在し、素子が別の電気部品に軸方向に取り付けられるように適応される、素子。 - 前記第1および第2の軸方向に延在する電気リードは共通の長手方向軸に沿って延在し、前記上部および下部ダイパッドは前記長手方向軸を含む平面に延在する、請求項1に記載の軸方向に取り付け可能な素子。
- 前記上部および下部ダイパッドは、それぞれ前記第1および第2の軸方向に延在する電気リードにはんだ接合によって接続する、請求項1に記載の軸方向に取り付け可能な素子。
- 前記上部および下部ダイパッドは、それぞれ前記第1および第2の軸方向に延在する電気リードに接続されるレーザ溶接部を備える、請求項1に記載の軸方向に取り付け可能な素子。
- 前記上部ダイパッドは上部平面に延在し、前記下部ダイパッドは下部平面に延在し、前記上部および下部平面は互いに平行であり、互いにずれている、請求項1に記載の軸方向に取り付け可能な素子。
- 前記半導体チップは前記上部平面と下部平面との間に位置する、請求項5に記載の軸方向に取り付け可能な素子。
- 前記パッケージング素材は円筒形の構成を有するハウジングである、請求項1に記載の軸方向に取り付け可能な素子。
- 前記第1および第2の軸方向に延在する電気リードは共通の長手方向軸に沿って延在し、 前記ハウジングは前記共通の長手方向軸に平行な円筒形の軸を有する、請求項7に記載の軸方向に取り付け可能な素子。
- 前記パッケージング素材は長方形の構成を有するハウジングである、請求項1に記載の軸方向に取り付け可能な素子。
- 前記半導体チップは出力ダイオードである、請求項1に記載の軸方向に取り付け可能な素子。
- 前記半導体チップは過渡電圧サプレッサである、請求項1に記載の軸方向に取り付け可能な素子。
- 前記半導体チップはLEDである、請求項1に記載の軸方向に取り付け可能な素子。
- 前記半導体チップは前記上部および下部ダイパッドにはんだ接合される、請求項1に記載の軸方向に取り付け可能な素子。
- 軸方向に取り付け可能な素子を形成する方法であって、
(a)下部ダイパッドを半導体チップの下部電気接点に電気的および機械的に接続することと、
(b)上部ダイパッドを前記半導体チップの上部電気接点に電気的および機械的に接続することと、
(c)第1の軸方向に延在する電気リードを前記上部ダイパッドに電気的および機械的に接続し、前記第1の軸方向に延在する電気リードは第1の軸方向に延在することと、
(d)第2の軸方向に延在する電気リードを前記下部ダイパッドに電気的および機械的に接続し、前記第2の軸方向に延在する電気リードは、前記第1の軸方向とは反対の第2の軸方向に延在することと、
(e)前記半導体チップ、前記上部および下部ダイパッド、前記第1および第2の軸方向に延在する電気リードの一部をパッケージング素材に封止することと、
を含み、
前記第1および第2の軸方向に延在する電気リードは、共通の平面に延在し、
前記第1および第2の軸方向に延在する電気リードは前記パッケージング素材から延在し、前記素子が別の電気部品に軸方向に取り付けられるように適応される、方法。 - 前記上部および下部ダイパッドを平面に延在するように配置することをさらに含み、前記平面は前記第1および第2の軸方向に延在する電気リードが延在する長手方向軸を含む、請求項14に記載の方法。
- 前記上部および下部ダイパッドを、前記第1および第2の軸方向に延在する電気リードにそれぞれはんだ接合によって接続することをさらに含む、請求項14に記載の方法。
- 前記上部および下部ダイパッドを、前記第1および第2の軸方向に延在する電気リードにそれぞれレーザ溶接によって接続することをさらに含む、請求項14に記載の方法。
- 請求項14に記載の方法であって、前記上部ダイパッドを上部平面に延在するように配置し、前記下部ダイパッドを下部平面に延在するように配置することをさらに含み、前記上部および下部平面は互いに平行であり、互いにずれている、方法。
- 前記半導体チップを前記上部平面と下部平面との間に配置することをさらに含む、請求項18に記載の方法。
- 前記パッケージング素材は円筒形の構成を有するハウジングである、請求項14に記載の方法。
- 前記第1および第2の軸方向に延在する電気リードは共通の長手方向軸に沿って延在し、 前記ハウジングの円筒形の軸を、前記共通の長手方向軸と平行になるように配置することをさらに含む、請求項20に記載の方法。
- 前記パッケージング素材は長方形の構成を有する、請求項14に記載の方法。
- 請求項16に記載の方法であって、前記はんだ接合を同時に形成することをさらに含み、前記はんだ接合は、前記上部および下部ダイパッドを前記半導体チップの前記上部および下部電気接点にそれぞれ接続する、方法。
- 請求項16に記載の方法であって、上部ダイパッドを前記半導体チップの上部電気接点に接続する前記はんだ接合を形成する前に、前記下部ダイパッドを前記半導体チップの前記下部電気接点に接続する前記はんだ接合を形成することをさらに含む、方法。
- 請求項24に記載の方法であって、前記下部ダイパッドを前記下部電気接点に接続する前記はんだ接合は、前記上部ダイパッドを前記半導体チップの前記上部電気接点に接続する前記はんだ接合を形成するために用いるはんだよりも溶融温度が高いはんだから形成される、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/674,006 US9041188B2 (en) | 2012-11-10 | 2012-11-10 | Axial semiconductor package |
US13/674,006 | 2012-11-10 | ||
PCT/US2012/070402 WO2014074120A1 (en) | 2012-11-10 | 2012-12-18 | Axial semiconductor package |
Publications (3)
Publication Number | Publication Date |
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JP2015534286A JP2015534286A (ja) | 2015-11-26 |
JP2015534286A5 JP2015534286A5 (ja) | 2016-01-14 |
JP6245266B2 true JP6245266B2 (ja) | 2017-12-20 |
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Application Number | Title | Priority Date | Filing Date |
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JP2015541755A Expired - Fee Related JP6245266B2 (ja) | 2012-11-10 | 2012-12-18 | 半導体アキシャルパッケージ |
Country Status (7)
Country | Link |
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US (1) | US9041188B2 (ja) |
EP (1) | EP2917936B1 (ja) |
JP (1) | JP6245266B2 (ja) |
KR (1) | KR20150063154A (ja) |
CN (1) | CN104813467B (ja) |
TW (2) | TWI518851B (ja) |
WO (1) | WO2014074120A1 (ja) |
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US10163762B2 (en) * | 2015-06-10 | 2018-12-25 | Vishay General Semiconductor Llc | Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting |
CN108406149B (zh) * | 2018-01-31 | 2020-04-24 | 常州志得电子有限公司 | 焊接方法 |
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US3621114A (en) * | 1969-08-19 | 1971-11-16 | Twr Semiconductors Inc | Lead frame configuration |
US5166098A (en) * | 1988-03-05 | 1992-11-24 | Deutsche Itt Industries Gmbh | Method of manufacturing an encapsulated semiconductor device with a can type housing |
US5232463A (en) * | 1988-03-05 | 1993-08-03 | Deutsche Itt Industries Gmbh | Apparatus for manufacturing a semiconductor device |
JP2620355B2 (ja) * | 1988-03-05 | 1997-06-11 | ドイチエ・アイティーティー・インダストリーズ・ゲゼルシャフト・ミト・ベシュレンクタ・ハフツンク | 半導体装置の製造方法および製造装置 |
EP0408779B1 (en) | 1989-07-18 | 1993-03-17 | International Business Machines Corporation | High density semiconductor memory module |
US5327318A (en) * | 1992-12-07 | 1994-07-05 | Texas Instruments Incorporated | Telecommunication equipment protector |
JP3329073B2 (ja) * | 1993-06-04 | 2002-09-30 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
US5506174A (en) * | 1994-07-12 | 1996-04-09 | General Instrument Corp. | Automated assembly of semiconductor devices using a pair of lead frames |
KR100186309B1 (ko) | 1996-05-17 | 1999-03-20 | 문정환 | 적층형 버텀 리드 패키지 |
JP3937265B2 (ja) | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | 半導体装置 |
KR100379600B1 (ko) | 2000-08-14 | 2003-04-10 | 삼성전자주식회사 | 듀얼 칩 패키지의 제조 방법 |
TW565925B (en) | 2000-12-14 | 2003-12-11 | Vanguard Int Semiconduct Corp | Multi-chip semiconductor package structure process |
JP4321742B2 (ja) * | 2002-03-26 | 2009-08-26 | ローム株式会社 | 半導体チップを使用した半導体装置 |
US6919625B2 (en) * | 2003-07-10 | 2005-07-19 | General Semiconductor, Inc. | Surface mount multichip devices |
TWM273822U (en) * | 2004-06-29 | 2005-08-21 | Super Nova Optoelectronics Cor | Surface mounted LED leadless flip chip package having ESD protection |
JP4676285B2 (ja) * | 2005-08-30 | 2011-04-27 | セイコーインスツル株式会社 | 表面実装型圧電振動子とその製造方法、発振器、電子機器及び電波時計 |
CN102473653B (zh) * | 2010-02-01 | 2016-05-04 | 丰田自动车株式会社 | 半导体装置的制造方法以及半导体装置 |
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US9041188B2 (en) | 2015-05-26 |
TW201419456A (zh) | 2014-05-16 |
TWI518851B (zh) | 2016-01-21 |
CN104813467B (zh) | 2019-03-08 |
CN104813467A (zh) | 2015-07-29 |
JP2015534286A (ja) | 2015-11-26 |
US20140131842A1 (en) | 2014-05-15 |
TWI582914B (zh) | 2017-05-11 |
WO2014074120A1 (en) | 2014-05-15 |
TW201604999A (zh) | 2016-02-01 |
KR20150063154A (ko) | 2015-06-08 |
EP2917936A4 (en) | 2016-07-13 |
EP2917936A1 (en) | 2015-09-16 |
EP2917936B1 (en) | 2021-02-03 |
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