CN104813467B - 轴向半导体封装 - Google Patents

轴向半导体封装 Download PDF

Info

Publication number
CN104813467B
CN104813467B CN201280076976.6A CN201280076976A CN104813467B CN 104813467 B CN104813467 B CN 104813467B CN 201280076976 A CN201280076976 A CN 201280076976A CN 104813467 B CN104813467 B CN 104813467B
Authority
CN
China
Prior art keywords
die pad
lead
lower die
chip
upper die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201280076976.6A
Other languages
English (en)
Other versions
CN104813467A (zh
Inventor
江挽澜
彭智平
丁慧英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay General Semiconductor LLC
Original Assignee
Vishay General Semiconductor LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vishay General Semiconductor LLC filed Critical Vishay General Semiconductor LLC
Publication of CN104813467A publication Critical patent/CN104813467A/zh
Application granted granted Critical
Publication of CN104813467B publication Critical patent/CN104813467B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335—Material
    • H01L2224/33505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

可轴向安装装置包括包含下和上电触点的半导体芯片。将下裸片垫电连接且机械连接到芯片的下电触点。将上裸片垫电连接且机械连接到芯片的上电触点。第一轴向延伸电引线电连接且机械连接到上裸片垫并在第一轴向方向上延伸。第二轴向延伸电引线电连接且机械连接到下裸片垫并在与第一轴向方向相反的第二轴向方向上延伸。封装材料包封半导体芯片、上和下裸片垫以及第一和第二轴向延伸引线的一部分。第一和第二引线从封装材料延伸并适于允许该装置与另一电部件轴向安装。

Description

轴向半导体封装
背景
轴向封装用于包封各种各样的裸片或芯片。有许多不同类型的轴向封装可用，其中的多种已经标准化。例如，DO-41是常常用于包封大功率二极管诸如在整流器中使用的那些二极管的封装。通常由JEDEC固态技术协会标准化的标准化轴向封装的其它示例包括DO-15、DO201AD和P600。
图1a和图1b示出了典型的轴向封装10的示例。图1a示出了为了组装而被对准的部件，并且图1b示出了组装之后的部件。该封装10包括裸片或芯片15、焊片20以及引线25，该引线25在一端以引线头30终结。如图所示，该芯片位于引线头30之间，并且该芯片在经受了高温回流工艺之后被焊片20接合在一起，在高温回流工艺期间熔化焊料。在将部件接合在一起之后它们经受模制工艺以将它们包封在由模制材料形成的圆柱体内。
在图1a和1b中示出的轴向封装设计具有许多缺点。例如，如图1a中所示，这些部件需要小心地装载并且彼此对准。由于该工艺的属性，所以难以针对零件堆叠采用自动化工艺，并且因此通常采用手动工艺。另一缺点是：不同尺寸的芯片需要具有不同尺寸引线头的引线，具有不同尺寸引线头的引线继而需要在其中堆叠且对准这些部件的不同尺寸组件。单一尺寸的引线头不能用于不同尺寸的芯片，因为引线头应当完全覆盖芯片以使该芯片免受机械损伤。然而，引线头不应过大，因为这将会导致对准问题。出于该相同原因，在其中将这些部件对准的单一尺寸组件是不实用的。因此，每次选择新的芯片尺寸，所有相关部件就必须被改变。作为结果，需要维持大库存的引线头和组件。
当前的轴向封装设计的另一缺点是：可能有拙劣的焊料润湿性，这是因为由于这些部件过于脆弱而不能经受助焊剂清理工艺而使得焊料助焊剂工艺不能用于将这些部件接合。不使用助焊剂，可能产生显著的焊料空洞。为了克服该问题，常将子组件暴露于回流或真空炉中的还原性气氛。然而，需要细心管理该炉的控制和维护。而且，焊料回流工艺是在其中存在有许多将会影响到焊接品质的因素的手动工艺。这些因素包括温度分布、气体环境以及被同时放置在该炉中的子组件的数目。因为这些因素中的每个均可能会改变，因此在最终的装置当中可能会存在批次间的不一致性。
因此，期望提供克服前述问题的一种轴向封装设计。
发明内容
根据本发明的一个方面，提供一种可轴向安装装置。该装置包括包含下和上电触点的半导体芯片。将下裸片垫电连接且机械连接到芯片的下电触点。将上裸片垫电连接且机械连接到芯片的上电触点。第一轴向延伸电引线电连接且机械连接到上裸片垫并在第一轴向方向上延伸。第二轴向延伸电引线电连接且机械连接到下裸片垫并在与第一轴向方向相反的第二轴向方向上延伸。封装材料包封半导体芯片、上和下裸片垫以及第一和第二轴向延伸引线的一部分。第一和第二引线从封装材料延伸并适于允许该装置与另一电部件轴向安装。
附图的简要说明
图1a示出了为了组装而被对准的常规轴向封装的一个示例的部件，而图1b示出了组装之后的常规轴向封装。
图2示出了容置电子部件例如半导体裸片或芯片的轴向封装的一个示例的横截面图。
图3是示出了用于生产可轴向安装装置的工艺的一个示例的流程图。
详细说明
图2示出了容置电子部件例如半导体裸片或芯片的轴向封装的一个示例的横截面图。该芯片或裸片可以是任何类型的电极装置，例如功率二极管、瞬态电压抑制器、LED等。如图所示，将芯片115焊接到第一裸片垫120的表面，以便在第一裸片垫120与在芯片115的下表面上的电极之间建立电接触。第一裸片垫120在与纵向或轴向轴线平行的平面中延伸，该纵向或轴向轴线贯穿正在被制造的得到的轴向封装。同样地，将芯片115焊接到第二裸片垫130的表面，以便在第二裸片垫130与在芯片115的上表面上的电极之间建立电接触。第二裸片垫130也在与贯穿正在被制造的生成轴向封装的该纵向或轴向轴线平行的平面中延伸。作为结果，芯片115也在轴向或纵向方向上延伸。裸片垫和引线可以由任何合适的导电材料例如铜形成。
将第一电裸片垫120电连接到第一轴向延伸引线125，并将第二电裸片垫130电连接到第二轴向延伸引线135。在某些实施例中，可以采用焊料接头或激光焊接建立所述电连接。在另一实施例中，可以将裸片垫及它们相应的引线一体地形成为单个引线框架。将裸片垫120和130以及引线125和135全部取向在轴向方向上。然而，它们彼此偏移，使得裸片垫120和130在不同但平行的平面中延伸至引线125和135在其中延伸的平面。这样裸片垫120和130彼此充分地接近，使得每一个均接触裸片115的相应表面。
完成结构包括外壳140，该外壳140将芯片115以及裸片垫120和130完全包封。第一轴向延伸引线125和第二轴向延伸引线135从装置外壳140侧向地向外延伸，以允许电连接到外部装置。在所示实施例中，引线125和135在公共平面中在相反方向上从装置延伸，但这绝不是必要的。在一个实施方式中，外壳140具有符合标准轴向封装设计的大体圆柱形构造。然而，该外壳也可以具有其它形状。例如，在某些情形中长方外壳在某些应用中可能是有利的。
在制造期间，通过首先将焊料层施加到裸片垫120并将芯片115放置在裸片垫120上，而将芯片115典型地焊料结合到裸片垫120和130。该芯片的未结合上表面于是能够设有焊料层。然后该裸片垫130能够设置在芯片115的顶部上，并且在高温回流工艺中将生成的组件加热至合适的熔合温度。这样，半导体芯片115与裸片垫120之间的结合以及半导体芯片115与裸片垫130之间的结合能够同时形成。
在另一实施方式中，能够首先形成半导体芯片115与裸片垫120之间的结合，接着形成半导体芯片115与裸片垫130之间的结合。在此实施方式中，在芯片的上表面上使用的焊料能够具有比在芯片的下表面上使用的焊料低的熔合温度。这将有助于防止来自上表面结合工艺的热将之前制作的下表面结合软化。
能够根据在使用引线框架的装置的制造中所使用的已知技术来执行后续工艺。例如，生成的组件可以设置在模具中，并且能够在压力下将封装材料例如环氧树脂强制进入到该模具中。该材料将在芯片和裸片垫周围流动并将芯片和裸片垫完全包封。在树脂硬化时及模具打开时，该装置将包括固体树脂包封140，该固体树脂包封140具有从固体树脂包封140延伸的轴向引线125和135。
上述轴向组件设计产生许多优点。首先，上述轴向组件允许合并零件及裸片库存。不再需要在制造图1所示的装置时所涉及的几乎所有轴向零件和工具。不再需要的物品包括不同尺寸的引线头和容纳不同芯片尺寸的堆叠船形器皿、裸片摇动装载器以及回流炉。唯一需要在库存中维持的轴向零件是直径稍微不同的端子引线。该轴向组件所需要的所有其余部件和裸片共享表面安装生产线，从而产生潜在的巨大成本节约。
另一优点是制造工艺能够容易地自动化。因此，以与表面安装裸片焊接工艺类似的自动工艺替代用于形成轴向封装的常规手动装载和堆叠工艺。此外，还消除了炉回流步骤中所需的手动装载。
由上述轴向组件设计所产生的又一优点是能够更好的维持一致的品质控制。这部分地因为用于裸片焊接和清理的助焊剂的使用能够提供较好的焊料润湿性和较少的焊料空洞。自动工艺的属性也降低了批次间不一致性的可能性。
此外，用于制造上述轴向组件设计的工艺能够容易地适应设计变化。例如，当芯片尺寸改变时，不必重新设计裸片垫和堆叠船形器皿。已有的表面安装封装例如SMA、SMB和SMC，每一个均适应某个范围的芯片尺寸。在芯片尺寸的改变需要不同裸片垫以及芯片尺寸从一个封装到另一封装(例如从SMC至SMB)改变的情况下，这种改变仍然可以在新的工艺中发生。只要子组件匹配并连接至具有适当直径的引线，就可模制该子组件以形成任何轴向封装。因此，制造工艺相对于设计变化是非常灵活的。
在某些实施方式中，轴向引线可以是预镀Sn引线，可以通过激光焊接将该预镀Sn引线接合至裸片垫。这样所生成的轴向部件将不需要另一引线镀层。作为结果，可以降低电镀成本。此外，在电镀工艺期间没有引线变形的风险。作为结果，能够维持高的组件产量，这导致了较低制造成本。
图3是示出了用于生产可轴向安装装置的工艺的一个示例的流程图。该方法在步骤310开始，在步骤310时，将第一轴向延伸引线电连接且机械连接到下裸片垫。此外，在步骤320中，将第二轴向延伸引线电连接且机械连接到上裸片垫。在步骤330中，将半导体芯片焊料结合至下裸片垫。在步骤340中将焊料施加至芯片的上表面，并且在步骤350中将上裸片垫焊料结合至下裸片垫。最后，在步骤360利用封装材料包封芯片和裸片垫。
用于生产可轴向安装装置的工艺的另一示例的流程在步骤410开始，在步骤410时，将半导体芯片焊料结合至下裸片垫。在步骤420中将焊料施加至芯片的上表面，并且在步骤430中将上裸片垫焊料结合至下裸片垫。在步骤440中，将第一轴向延伸引线电连接且机械连接到下裸片垫。此外，在步骤450中，将第二轴向延伸引线电连接且机械连接到上裸片垫。最后，在步骤460中，用封装材料包封芯片和裸片垫。
当然，如前所述在其它实施方式中，半导体芯片115与裸片垫120之间的结合以及半导体芯片115与裸片垫130之间的结合能够同时形成。该方法的一个优点是：用于将芯片115结合至裸片垫120的焊料可以具有与用于将芯片结合至裸片垫130的焊料相同的熔合温度。
以上示例和公开内容意图是说明性的而非穷举性的。这些示例和说明将为本领域技术人员建议许多变体和替代物。所有这些替代物和变体意图被包含在所附权利要求的范围内。熟知本技术的人员可以认识到在此所描述的具体实施例的其它等同物，这些其它等同物也意图被在此所附的权利要求所包含。

Claims (11)

1.一种形成可轴向安装装置的方法，包括：
(a)提供下裸片垫和上裸片垫，所述下裸片垫和所述上裸片垫彼此电分离且机械分离；
(b)将所述下裸片垫电连接且机械连接到半导体芯片的下电触点；
(c)将所述上裸片垫电连接且机械连接到所述半导体芯片的上电触点；
(d)将第一引线电连接且机械连接到所述上裸片垫，所述第一引线在第一轴向方向上延伸；
(e)将第二引线电连接且机械连接到所述下裸片垫，所述第二引线在与所述第一轴向方向相反的第二轴向方向上延伸；
(f)使用模制工艺将所述半导体芯片、所述上裸片垫和所述下裸片垫以及所述第一引线和所述第二引线的一部分包封在封装材料中；
其中所述第一引线和所述第二引线从所述封装材料延伸，并且所述第一引线和所述第二引线适于允许所述装置与另一电部件轴向安装；并且
其中布置所述下裸片垫和所述上裸片垫，使得所述下裸片垫和所述上裸片垫在与纵向轴线平行的平面中延伸，所述第一引线和所述第二引线在所述纵向轴线上延伸。
2.根据权利要求1所述的方法，进一步包括：通过焊料接头将所述上裸片垫连接到所述第一引线；和通过焊料接头将所述下裸片垫连接到所述第二引线。
3.根据权利要求1所述的方法，进一步包括：通过激光焊接将所述上裸片垫连接到所述第一引线；和通过激光焊接将所述下裸片垫连接到所述第二引线。
4.根据权利要求1所述的方法，进一步包括：布置所述上裸片垫使得所述上裸片垫在上平面中延伸，并且布置所述下裸片垫使得所述下裸片垫在下平面中延伸，其中所述上平面和所述下平面彼此平行且彼此偏移。
5.根据权利要求4所述的方法，进一步包括将所述半导体芯片定位在所述上平面和所述下平面之间。
6.根据权利要求1所述的方法，其中所述封装材料是具有圆柱形构造的外壳。
7.根据权利要求6所述的方法，进一步包括：布置所述外壳的圆柱轴线，使得所述外壳的所述圆柱轴线平行于公共纵向轴线。
8.根据权利要求1所述的方法，其中所述封装材料是具有长方构造的外壳。
9.根据权利要求2所述的方法，进一步包括：同时形成将所述上裸片垫连接到所述半导体芯片的所述上电触点的所述焊料接头和将所述下裸片垫连接到所述半导体芯片的所述下电触点的所述焊料接头。
10.根据权利要求2所述的方法，进一步包括：在形成将所述上裸片垫连接至所述半导体芯片的上电触点的所述焊料接头之前，形成将所述下裸片垫连接至所述半导体芯片的所述下电触点的所述焊料接头。
11.根据权利要求10所述的方法，其中由具有比用于形成将所述上裸片垫连接至所述半导体芯片的所述上电触点的所述焊料接头的焊料高的熔合温度的焊料形成将所述下裸片垫连接至所述下电触点的所述焊料接头。
CN201280076976.6A 2012-11-10 2012-12-18 轴向半导体封装 Expired - Fee Related CN104813467B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/674,006 2012-11-10
US13/674,006 US9041188B2 (en) 2012-11-10 2012-11-10 Axial semiconductor package
PCT/US2012/070402 WO2014074120A1 (en) 2012-11-10 2012-12-18 Axial semiconductor package

Publications (2)

Publication Number Publication Date
CN104813467A CN104813467A (zh) 2015-07-29
CN104813467B true CN104813467B (zh) 2019-03-08

Family

ID=50680927

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280076976.6A Expired - Fee Related CN104813467B (zh) 2012-11-10 2012-12-18 轴向半导体封装

Country Status (7)

Country Link
US (1) US9041188B2 (zh)
EP (1) EP2917936B1 (zh)
JP (1) JP6245266B2 (zh)
KR (1) KR20150063154A (zh)
CN (1) CN104813467B (zh)
TW (2) TWI582914B (zh)
WO (1) WO2014074120A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163762B2 (en) * 2015-06-10 2018-12-25 Vishay General Semiconductor Llc Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting
CN108406149B (zh) * 2018-01-31 2020-04-24 常州志得电子有限公司 焊接方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5232463A (en) * 1988-03-05 1993-08-03 Deutsche Itt Industries Gmbh Apparatus for manufacturing a semiconductor device
US5506174A (en) * 1994-07-12 1996-04-09 General Instrument Corp. Automated assembly of semiconductor devices using a pair of lead frames
CN1624889A (zh) * 1997-09-29 2005-06-08 株式会社日立制作所 半导体器件及其制造方法
CN102473653A (zh) * 2010-02-01 2012-05-23 丰田自动车株式会社 半导体装置的制造方法以及半导体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621114A (en) * 1969-08-19 1971-11-16 Twr Semiconductors Inc Lead frame configuration
JP2620355B2 (ja) * 1988-03-05 1997-06-11 ドイチエ・アイティーティー・インダストリーズ・ゲゼルシャフト・ミト・ベシュレンクタ・ハフツンク 半導体装置の製造方法および製造装置
US5166098A (en) * 1988-03-05 1992-11-24 Deutsche Itt Industries Gmbh Method of manufacturing an encapsulated semiconductor device with a can type housing
EP0408779B1 (en) 1989-07-18 1993-03-17 International Business Machines Corporation High density semiconductor memory module
US5327318A (en) * 1992-12-07 1994-07-05 Texas Instruments Incorporated Telecommunication equipment protector
JP3329073B2 (ja) * 1993-06-04 2002-09-30 セイコーエプソン株式会社 半導体装置およびその製造方法
KR100186309B1 (ko) 1996-05-17 1999-03-20 문정환 적층형 버텀 리드 패키지
KR100379600B1 (ko) 2000-08-14 2003-04-10 삼성전자주식회사 듀얼 칩 패키지의 제조 방법
TW565925B (en) 2000-12-14 2003-12-11 Vanguard Int Semiconduct Corp Multi-chip semiconductor package structure process
JP4321742B2 (ja) * 2002-03-26 2009-08-26 ローム株式会社 半導体チップを使用した半導体装置
US6919625B2 (en) * 2003-07-10 2005-07-19 General Semiconductor, Inc. Surface mount multichip devices
TWM273822U (en) * 2004-06-29 2005-08-21 Super Nova Optoelectronics Cor Surface mounted LED leadless flip chip package having ESD protection
JP4676285B2 (ja) * 2005-08-30 2011-04-27 セイコーインスツル株式会社 表面実装型圧電振動子とその製造方法、発振器、電子機器及び電波時計

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5232463A (en) * 1988-03-05 1993-08-03 Deutsche Itt Industries Gmbh Apparatus for manufacturing a semiconductor device
US5506174A (en) * 1994-07-12 1996-04-09 General Instrument Corp. Automated assembly of semiconductor devices using a pair of lead frames
CN1624889A (zh) * 1997-09-29 2005-06-08 株式会社日立制作所 半导体器件及其制造方法
CN102473653A (zh) * 2010-02-01 2012-05-23 丰田自动车株式会社 半导体装置的制造方法以及半导体装置

Also Published As

Publication number Publication date
TW201419456A (zh) 2014-05-16
WO2014074120A1 (en) 2014-05-15
EP2917936B1 (en) 2021-02-03
EP2917936A1 (en) 2015-09-16
EP2917936A4 (en) 2016-07-13
TW201604999A (zh) 2016-02-01
JP2015534286A (ja) 2015-11-26
CN104813467A (zh) 2015-07-29
JP6245266B2 (ja) 2017-12-20
US20140131842A1 (en) 2014-05-15
US9041188B2 (en) 2015-05-26
TWI518851B (zh) 2016-01-21
KR20150063154A (ko) 2015-06-08
TWI582914B (zh) 2017-05-11

Similar Documents

Publication Publication Date Title
JP5975911B2 (ja) 半導体装置
CN105765716B (zh) 功率半导体模块和复合模块
US10008394B2 (en) Method for mounting an electrical component, wherein a hood is used, and hood suitable for use in said method
US9589873B2 (en) Leadless chip carrier
JP6945418B2 (ja) 半導体装置および半導体装置の製造方法
CN104966710B (zh) 接触元件、功率半导体模块及其制造方法
CN107636828A (zh) 集成的夹具和引线以及制作电路的方法
CN104813467B (zh) 轴向半导体封装
JP2018517302A (ja) クリップシフトを低減させつつ半導体ダイを取り付けるための導電性クリップを具備するリードフレーム
JP2010092918A (ja) 板状電極とブロック状電極との接続構造及び接続方法
JP6391430B2 (ja) 電子制御装置およびその製造方法
JP2014003258A (ja) 半導体装置およびその製造方法
CN104112733A (zh) 用于封装半导体芯片的模制材料和方法
CN103559967B (zh) 贴片式无源电子元件安装结构和方法
JP2015534286A5 (zh)
CN108735614B (zh) 半导体装置及半导体装置的制造方法
CN112510005A (zh) 智能功率模块和智能功率模块的封装方法
CN203552830U (zh) 贴片式无源电子元件安装结构
CN102201379B (zh) 器件封装结构及其封装方法
CN104471705B (zh) 用于大面积半导体芯片的低热应力封装
CN212907718U (zh) 智能功率模块
JP2012033794A (ja) 半導体装置およびその製造方法
US20230146666A1 (en) Electronic package and method for manufacturing the same
CN108288608B (zh) 芯片封装体及其制备方法
CN113299616A (zh) 半导体器件的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190308

CF01 Termination of patent right due to non-payment of annual fee