TWI582914B - 軸向半導體封裝 - Google Patents
軸向半導體封裝 Download PDFInfo
- Publication number
- TWI582914B TWI582914B TW104135840A TW104135840A TWI582914B TW I582914 B TWI582914 B TW I582914B TW 104135840 A TW104135840 A TW 104135840A TW 104135840 A TW104135840 A TW 104135840A TW I582914 B TWI582914 B TW I582914B
- Authority
- TW
- Taiwan
- Prior art keywords
- die pad
- lead
- semiconductor wafer
- lower die
- electrically
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000000034 method Methods 0.000 claims description 32
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 10
- 238000005476 soldering Methods 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 47
- 230000008569 process Effects 0.000 description 18
- 238000013461 design Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 230000004927 fusion Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/335—Material
- H01L2224/33505—Layer connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係有關軸向半導體封裝。
軸向封裝用於封裝各式各樣的晶粒或晶片。有許多不同種類的軸向封裝可用,許多軸向封裝已標準化。例如,DO-41係常用於封裝大功率二極體,諸如,使用在整流器中的二極體,的封裝。通常由JEDEC固態技術協會標準化的標準化軸向封裝的其他範例包括DO-15、DO-201AD、及P600。
圖1a及1b顯示典型軸向封裝10的範例。圖1a顯示針對組裝對齊的組件,且圖1b顯示組裝之後的組件。封裝10包括晶粒或晶片15、焊片20、及以引線接頭30終結於一端上的引線25。如圖所示,該晶片位於引線接頭30之間,並在受焊料於期間熔化的高溫回流處理之後藉由焊片20接合在一起。在將組件接合在一起之後,彼等受成型處理以將彼等封裝在從成型化合物形成的圓柱體內。
顯示在圖1a及1b中的軸向封裝設計具有許多缺點。例如,如圖1a所示,該等組件必需細心地裝載及彼此對準。由於此處理的本質,難以針對零件堆疊採用自動處理,且因此通常使用手動處理。其他缺點係不同尺寸的晶片需要具有不同尺寸引線接頭的引線,其反而需要於其中堆疊及對準該等組件的不同尺寸配件。單一尺寸的引線接頭不能用於不同尺寸的晶片,因為其應完全覆蓋該晶片以防止其受機械損壞。然而,引線接頭不應過大,因為會導致對準問題。為此相同原因,於其中將該等組件對準的單一尺寸配件係不實際的。因此,每次選擇新的晶片尺寸,就必需改變所有相關組件。結果必需維持引線接頭及配件的大量存貨。
目前的軸向封裝設計的另一缺點係可能有拙劣的焊料潤濕,因為該等組件太過脆弱而不能通過助焊劑清洗處理,不能使用焊接助熔劑處理接合彼等。不能使用助焊劑,可能引發顯著的焊料空隙。為克服此問題,常將次配件暴露於回流或真空爐中的還原性大氣中。然而,必需細心地管理該爐的控制及維護。再者,焊料回流處理係在其中有許多會影響焊接品質之因素的手動處理。此等因素包括溫度分佈、氣體大氣、及同時放置在該爐中之次配件的數量。因為此等因素各者可能改變,在最終裝置之間的可能有批次間的不一致性。
因此,會期望提供克服上述問題的軸向封裝設計。
依據本發明的一實施樣態,提供一種可軸向載置裝置。該裝置包括包含下及上電接點的半導體晶片。將下晶粒焊墊電性地及機械地連接至該晶片的該下電接點。將上晶粒焊墊電性地及機械地連接至該晶片的該上電接點。將第一軸向延伸電引線電性地及機械地連接至該上晶粒焊墊並在該第一軸方向上延伸。將第二軸向延伸電引線電性地及機械地連接至該下晶粒焊墊並在與該第一軸方向相反的第二軸方向上延伸。封裝材料密封該半導體晶片、該等上及下晶粒焊墊、及該等第一及第二軸向延伸引線的一部分。該等第一及第二引線從該封裝材料延伸,並適於容許該裝置軸向載置有另一電組件。
10‧‧‧軸向封裝
15‧‧‧晶粒或晶片
20‧‧‧焊片
25‧‧‧引線
30‧‧‧引線接頭
115‧‧‧晶片
120‧‧‧第一晶粒焊墊
125‧‧‧第一軸向延伸引線
130‧‧‧第二晶粒焊墊
135‧‧‧第二軸向延伸引線
140‧‧‧外殼
圖1a顯示針對組裝對準之習知軸向封裝的一範例的組件,且圖1b顯示組裝後的習知軸向封裝。
圖2顯示收容電子組件,諸如,半導體晶粒或晶片,的軸向封裝之一範例的橫剖面圖。
圖3係顯示用於產生可軸向載置裝置的處理之一範例的流程圖。
圖4係顯示用於產生可軸向載置裝置的處理之另一範例的流程圖。
圖2顯示收容電子組件,諸如,半導體晶粒或晶片,的軸向封裝之一範例的橫剖面圖。該晶片或晶粒可能係何任種類的電極裝置,諸如,功率二極體、暫態電壓抑制器、LED等。如圖所描繪的,將晶片115焊接至第一晶粒焊墊120的表面,以在第一晶粒焊墊120及在晶片115之下表面上的電極之間建立電接觸。第一晶粒焊墊120在平行於通過正在製造之產生的軸向封裝之縱向或軸向軸的平面中延伸。相似地,將晶片115焊接至第二晶粒焊墊130的表面,以在第二晶粒焊墊130及在晶片115之上表面上的電極之間建立電接觸。第二晶粒焊墊130也在平行於通過正在製造之產生的軸向封裝之縱向或軸向軸的平面中延伸。結果晶片115也在該軸向或縱向方向上延伸。晶粒焊墊及引線可能從任何合適的電性導通材料形成,諸如,銅。
將第一電晶粒焊墊120電性連接至第一軸向延伸引線125,並將第二電晶粒焊墊130電性連接至第二軸向延伸引線135。在部分實施例中,該等電性連接可能使用焊接或雷射熔接建立。在另一實施例中,可能將晶粒焊墊及彼等的個別引線積體地形成為單一引線框架。將晶粒焊墊120及130及引線125及135全部定向在軸向方向上。然而,彼等相互移位,使得晶粒焊墊120及130在不同但平行的平面上延伸至引線125及135於其中延伸的平面。以此方式,晶粒焊墊120及130彼此充分地接近,使得各者接觸晶粒115的個別表面。
已完成的結構包括外殼140,其完全封裝晶片115及晶粒焊墊120及130。第一及第二軸向延伸引線125及135從裝置外殼140側向地向外延伸,以容許電連接至外部裝置。在所說明的實施例中,引線125及135在共同平面中在相反方向上從該裝置延伸,但此絕非必要的。在一實作中,外殼140具有順應標準軸向封裝設計的一般圓柱組態。然而,該外殼也可能具有其他形狀。例如,在部分情形中,矩形外殼在部分應用可能係有利的。
在製造期間,藉由最先將焊料層施加至晶粒焊墊120並將晶片115放置在晶粒焊墊120上,將晶片115典型地焊接合至晶粒焊墊120及130。然後該晶片的未接合上表面可設置有焊料層。然後可將晶粒焊墊130設置在晶片115的頂部上,並在高溫回流處理中將產生的配件加熱至適當的熔合溫度。以此方式,半導體晶片115及晶粒焊墊120之間的接合及半導體晶片115及晶粒焊墊130之間的接合可同時形成。
在另一實作中,半導體晶片115及晶粒焊墊120之間的接合可最先形成,然後形成半導體晶片115及晶粒焊墊130之間的接合。在此實作中,使用在晶片之上表面上的焊料可具有比使用在晶片之下表面上的焊料更低的熔合溫度。此將協助防止來自上表面接合處理的熱軟化先前產生的下表面接合。
後續處理可依據在使用引線框架之裝置的製造中使用的已知技術實行。例如,可將產生的配件設置在
模具及在壓力下可強制進入該模具的封裝材料中,例如,環氧樹脂。該材料將在晶片及晶粒焊墊周圍流動並完全封裝彼等。在該樹脂硬化及該模具開啟時,該裝置將包含具有延伸自其之軸向引線125及135的固體樹脂封包140。
許多優點係由上文描述的軸向配件設計所引起。首先,其容許將零件及晶粒庫存整合。幾乎不再需要在製造圖1所示之裝置時所涉及的所有軸向零件及工具。不再需要的項目包括不同尺寸的引線接頭及容納不同晶片尺寸之不同尺寸的堆疊船形皿、晶粒搖動裝載器、及回流爐。唯一需要維持在庫存中的軸向零件係少數不同直徑的終端引線。此軸向組裝所需要的所有其餘組件及晶粒共享表面載置生產線,從而產生潛在的巨大成本節省。
另一優點係可輕易地將製程自動化。因此,以與表面載置晶粒焊接處理相似的自動處理取代用於形成軸向封裝的習知手動裝載及堆疊處理。此外,也消除爐回流步驟中所需要的手動裝載。
由上述軸向配件設計引起的另一優點係可更佳地維持一致的品質控制。部分因為用於晶粒焊接及清理之助焊劑的使用可提供更佳的焊料潤濕及較少的焊料空隙。自動處理的本質也降低批次間不一致性的可能性。
再者,用於製造上述軸向配件設計的處理可輕易地容納設計改變。例如,當晶片尺寸改變時,不必重設計晶粒焊墊及堆疊船形皿。諸如SMA、SMB、及SMC的既存表面載置封裝各者容納特定範圍的晶片尺寸。在晶
片尺寸改變需要不同晶粒焊墊及從一封裝改變至另一封裝(例如,從SMC改變至SMB)的事件中,此種改變仍可發生在新處理中。只要次配件匹配並連接至具有適當直徑的引線,可將其成型以形成任何軸向封裝。因此,製程可相關於設計改變非常有彈性。
在部分實作中,軸向引線可係預鍍Sn引線,其可藉由雷射熔接接合至晶粒焊墊。以此方式,產生的軸向組件將不需要其他電鍍引線。結果,可降低電鍍成本。再者,在電鍍處理期間沒有引線形變的風險。結果,可維持高配件良率,導致較低的製造成本。
圖3係顯示用於產生可軸向載置裝置的處理之一範例的流程圖。該方法在步驟310開始,其中將第一軸向延伸引線電性及機械地連接至下晶粒焊墊。此外,在步驟320中,將第二軸向延伸引線電性及機械地連接至上晶粒焊墊。在步驟330中,將半導體晶片焊接合至下晶粒焊墊。在步驟340中,將焊料施加至晶片的上表面,並在步驟350中,將該上晶粒焊墊焊接合至下晶粒焊墊。最終,在步驟360中,以封裝材料封裝晶片及晶粒焊墊。
圖4係顯示用於產生可軸向載置裝置的處理之另一範例的流程圖。該方法在步驟410開始,其中將半導體晶片焊接合至下晶粒焊墊。在步驟420中,將焊料施加至晶片的上表面,並在步驟430中,將該上晶粒焊墊焊接合至下晶粒焊墊。在步驟440中,將第一軸向延伸引線電性及機械地連接至下晶粒焊墊。此外,在步驟450中,
將第二軸向延伸引線電性及機械地連接至上晶粒焊墊。最終,在步驟460中,以封裝材料封裝晶片及晶粒焊墊。
當然,如先前在其他實作中提及的,半導體晶片115及晶粒焊墊120之間的接合及半導體晶片115及晶粒焊墊130之間的接合可同時形成。此方式的一優點係用於將晶片115接合至晶粒焊墊120的焊料可能具有與用於將晶片接合至晶粒焊墊130之焊料相同的熔合溫度。
將上述範例及揭示內容視為係說明性而非徹底揭示。此等範例及描述對熟悉本技術的人士建議許多變化及改變。將所有此等改變及改變視為包括在隨附的申請專利範圍的範圍中。熟悉本技術的人士可能承認也將等效於本文描述之特定實施例的其他等效實例視為由隨附於此的申請專利範圍所包含。
115‧‧‧晶片
120‧‧‧第一晶粒焊墊
125‧‧‧第一軸向延伸引線
130‧‧‧第二晶粒焊墊
135‧‧‧第二軸向延伸引線
140‧‧‧外殼
Claims (11)
- 一種形成可軸向載置裝置的方法,包含:(a)將下晶粒焊墊電性地及機械地連接至半導體晶片的下電接點;(b)將上晶粒焊墊電性地及機械地連接至該半導體晶片的該上電接點;(c)將第一軸向延伸電引線電性地及機械地連接至該上晶粒焊墊,該第一引線在第一軸方向上延伸;(d)將第二軸向延伸電引線電性地及機械地連接至該下晶粒焊墊,該第二引線在與該第一軸方向相反的第二軸方向上延伸;(e)該半導體晶片、該等上及下晶粒焊墊及該等第一及第二軸向延伸引線的一部分密封在封裝材料中;且其中該等第一及第二引線從該封裝材料延伸,並適於容許該裝置軸向載置有另一電組件,及其中該等第一及第二軸向延伸引線沿著共同縱向軸延伸,且該等下及上晶粒焊墊在包括該縱向軸的平面中延伸。
- 如申請專利範圍第1項的方法,更包含藉由焊接將該等上及下晶粒焊墊分別連接至該等第一及第二引線。
- 如申請專利範圍第1項的方法,更包含藉由雷射熔接將該等上及下晶粒焊墊分別連接至該等第一及第二引線。
- 如申請專利範圍第1項的方法,更包含將該上晶粒 焊墊配置成使得其在上平面中延伸,並將該下晶粒焊墊配置成使得其在下平面中延伸,其中該等上及下平面彼此平行且彼此移位。
- 如申請專利範圍第4項的方法,更包含將該半導體晶片定位在該等上及下平面之間。
- 如申請專利範圍第1項的方法,其中該封裝材料係具有圓柱組態的外殼。
- 如申請專利範圍第6項的方法,更包含將該外殼的圓柱軸配置成使得其平行於該共同縱向軸。
- 如申請專利範圍第1項的方法,其中該封裝材料係具有矩形組態的外殼。
- 如申請專利範圍第2項的方法,更包含同時形成將該等上及下晶粒焊墊分別連接至該半導體晶片之該等上及下電接點的焊接。
- 如申請專利範圍第2項的方法,更包含在形成將該上晶粒焊墊連接至該半導體晶片之該上電接點的焊接之前形成將該下晶粒焊墊連接至該半導體晶片之該下電接點的焊接。
- 如申請專利範圍第10項的方法,其中該下晶粒焊墊連接至該下電接點引線形成之焊接所用的焊接劑比該上晶粒焊墊連接至該半導體晶片上電接點形成之焊接所用的焊接劑具有更高的熔融溫度。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/674,006 US9041188B2 (en) | 2012-11-10 | 2012-11-10 | Axial semiconductor package |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201604999A TW201604999A (zh) | 2016-02-01 |
TWI582914B true TWI582914B (zh) | 2017-05-11 |
Family
ID=50680927
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104135840A TWI582914B (zh) | 2012-11-10 | 2013-01-22 | 軸向半導體封裝 |
TW102102349A TWI518851B (zh) | 2012-11-10 | 2013-01-22 | 軸向半導體封裝 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102102349A TWI518851B (zh) | 2012-11-10 | 2013-01-22 | 軸向半導體封裝 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9041188B2 (zh) |
EP (1) | EP2917936B1 (zh) |
JP (1) | JP6245266B2 (zh) |
KR (1) | KR20150063154A (zh) |
CN (1) | CN104813467B (zh) |
TW (2) | TWI582914B (zh) |
WO (1) | WO2014074120A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10163762B2 (en) * | 2015-06-10 | 2018-12-25 | Vishay General Semiconductor Llc | Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting |
CN108406149B (zh) * | 2018-01-31 | 2020-04-24 | 常州志得电子有限公司 | 焊接方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5506174A (en) * | 1994-07-12 | 1996-04-09 | General Instrument Corp. | Automated assembly of semiconductor devices using a pair of lead frames |
US5554885A (en) * | 1993-06-04 | 1996-09-10 | Seiko Epson Corporation | Semiconductor device including means for dispersing and absorbing tensile forces acting on film tape |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3621114A (en) * | 1969-08-19 | 1971-11-16 | Twr Semiconductors Inc | Lead frame configuration |
US5166098A (en) * | 1988-03-05 | 1992-11-24 | Deutsche Itt Industries Gmbh | Method of manufacturing an encapsulated semiconductor device with a can type housing |
JP2620355B2 (ja) * | 1988-03-05 | 1997-06-11 | ドイチエ・アイティーティー・インダストリーズ・ゲゼルシャフト・ミト・ベシュレンクタ・ハフツンク | 半導体装置の製造方法および製造装置 |
US5232463A (en) * | 1988-03-05 | 1993-08-03 | Deutsche Itt Industries Gmbh | Apparatus for manufacturing a semiconductor device |
EP0408779B1 (en) | 1989-07-18 | 1993-03-17 | International Business Machines Corporation | High density semiconductor memory module |
US5327318A (en) * | 1992-12-07 | 1994-07-05 | Texas Instruments Incorporated | Telecommunication equipment protector |
KR100186309B1 (ko) | 1996-05-17 | 1999-03-20 | 문정환 | 적층형 버텀 리드 패키지 |
JP3937265B2 (ja) | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | 半導体装置 |
KR100379600B1 (ko) | 2000-08-14 | 2003-04-10 | 삼성전자주식회사 | 듀얼 칩 패키지의 제조 방법 |
TW565925B (en) | 2000-12-14 | 2003-12-11 | Vanguard Int Semiconduct Corp | Multi-chip semiconductor package structure process |
JP4321742B2 (ja) * | 2002-03-26 | 2009-08-26 | ローム株式会社 | 半導体チップを使用した半導体装置 |
US6919625B2 (en) * | 2003-07-10 | 2005-07-19 | General Semiconductor, Inc. | Surface mount multichip devices |
TWM273822U (en) * | 2004-06-29 | 2005-08-21 | Super Nova Optoelectronics Cor | Surface mounted LED leadless flip chip package having ESD protection |
JP4676285B2 (ja) * | 2005-08-30 | 2011-04-27 | セイコーインスツル株式会社 | 表面実装型圧電振動子とその製造方法、発振器、電子機器及び電波時計 |
JP5321600B2 (ja) * | 2010-02-01 | 2013-10-23 | トヨタ自動車株式会社 | 半導体装置の製造方法および半導体装置 |
-
2012
- 2012-11-10 US US13/674,006 patent/US9041188B2/en not_active Expired - Fee Related
- 2012-12-18 KR KR1020157011780A patent/KR20150063154A/ko not_active Application Discontinuation
- 2012-12-18 WO PCT/US2012/070402 patent/WO2014074120A1/en active Application Filing
- 2012-12-18 JP JP2015541755A patent/JP6245266B2/ja not_active Expired - Fee Related
- 2012-12-18 EP EP12887888.1A patent/EP2917936B1/en active Active
- 2012-12-18 CN CN201280076976.6A patent/CN104813467B/zh not_active Expired - Fee Related
-
2013
- 2013-01-22 TW TW104135840A patent/TWI582914B/zh not_active IP Right Cessation
- 2013-01-22 TW TW102102349A patent/TWI518851B/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5554885A (en) * | 1993-06-04 | 1996-09-10 | Seiko Epson Corporation | Semiconductor device including means for dispersing and absorbing tensile forces acting on film tape |
US5506174A (en) * | 1994-07-12 | 1996-04-09 | General Instrument Corp. | Automated assembly of semiconductor devices using a pair of lead frames |
Also Published As
Publication number | Publication date |
---|---|
EP2917936A1 (en) | 2015-09-16 |
WO2014074120A1 (en) | 2014-05-15 |
US20140131842A1 (en) | 2014-05-15 |
TW201604999A (zh) | 2016-02-01 |
EP2917936B1 (en) | 2021-02-03 |
CN104813467A (zh) | 2015-07-29 |
JP2015534286A (ja) | 2015-11-26 |
TW201419456A (zh) | 2014-05-16 |
CN104813467B (zh) | 2019-03-08 |
EP2917936A4 (en) | 2016-07-13 |
KR20150063154A (ko) | 2015-06-08 |
JP6245266B2 (ja) | 2017-12-20 |
US9041188B2 (en) | 2015-05-26 |
TWI518851B (zh) | 2016-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9780081B2 (en) | Chip package structure and manufacturing method therefor | |
US9589873B2 (en) | Leadless chip carrier | |
JP2013026627A (ja) | パワー素子パッケージモジュール及びその製造方法 | |
TWI680518B (zh) | 具有用於安裝半導體晶粒減少夾子移動之導體夾子的導線架 | |
JP5233853B2 (ja) | 半導体装置 | |
TWI582914B (zh) | 軸向半導體封裝 | |
US20150279770A1 (en) | Package, semiconductor device, and semiconductor module | |
JP2003060121A (ja) | 半導体集積回路パッケージおよびその製造方法 | |
US20100295160A1 (en) | Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof | |
KR101474189B1 (ko) | 집적회로 패키지 | |
JP5898575B2 (ja) | 半導体装置 | |
JP6381489B2 (ja) | 半導体装置の製造方法 | |
JP2015534286A5 (zh) | ||
JP2001110845A (ja) | フリップチップの実装構造 | |
TWI651827B (zh) | 無基板封裝結構 | |
CN104112733A (zh) | 用于封装半导体芯片的模制材料和方法 | |
CN102412241B (zh) | 半导体芯片封装件及其制造方法 | |
CN202042476U (zh) | 器件封装结构 | |
CN204303804U (zh) | 可拆卸、可组装的半导体封装体堆叠结构 | |
CN102201379B (zh) | 器件封装结构及其封装方法 | |
CN108288608B (zh) | 芯片封装体及其制备方法 | |
KR101697643B1 (ko) | 이형필름을 포함하는 반도체 패키지 및 이의 제조방법 | |
JP2020178032A (ja) | パワー半導体モジュール | |
CN104465606A (zh) | 可拆卸、可组装的半导体封装体堆叠结构及其制备方法 | |
JPH08203942A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |