JP6196589B2 - 半導体装置の製造方法および半導体製造装置 - Google Patents
半導体装置の製造方法および半導体製造装置 Download PDFInfo
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- JP6196589B2 JP6196589B2 JP2014152285A JP2014152285A JP6196589B2 JP 6196589 B2 JP6196589 B2 JP 6196589B2 JP 2014152285 A JP2014152285 A JP 2014152285A JP 2014152285 A JP2014152285 A JP 2014152285A JP 6196589 B2 JP6196589 B2 JP 6196589B2
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0118—Processes for the planarization of structures
- B81C2201/0123—Selective removal
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
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- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0118—Processes for the planarization of structures
- B81C2201/0125—Blanket removal, e.g. polishing
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- H01J2237/317—Processing objects on a microscale
- H01J2237/31701—Ion implantation
- H01J2237/31706—Ion implantation characterised by the area treated
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- H01J2237/31711—Ion implantation characterised by the area treated patterned using mask
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Description
図1(A)〜図1(C)は、参考例による半導体装置の製造方法を示す断面図である。半導体装置は、特に限定しないが、例えば、半導体メモリ、高速ロジックLSI、システムLSI、メモリ・ロジック混載LSI等でよい。
図3は、第1の実施形態による半導体装置の製造方法を示す平面図である。第1の実施形態では、被研磨膜20の表面領域のうち、半導体基板10の外周部Pexを除く領域(以下、中心部Pinともいう)に上記第1種類のドーパントを選択的に注入する。
図6は、第2の実施形態による半導体装置の製造方法を示す平面図である。第2の実施形態では、被研磨膜20の表面領域のうち、半導体基板10の外周部Pexに第2種類のドーパントを選択的に注入する。第2種類のドーパントは、例えば、炭素(C)、窒素(N)またはシリコン(Si)等でよい。イオン注入は、約1〜5.00×1015/cm2のドーズ量のドーパントを約50KeVの加速電圧で行われる。第2種類のドーパントは、スラリと被研磨膜20との反応を抑制する元素である。従って、第2種類のドーパントは、半導体基板10の外周部Pexにおける被研磨膜20の研磨速度を低下させるためにイオン注入される。
図8は、第3の実施形態による半導体装置の製造方法を示すフロー図である。第3の実施形態は、第2および第2の実施形態の組み合わせである。即ち、被研磨膜20の表面領域のうち、半導体基板10の中心部Pinに第1種類のドーパントを選択的に注入し、尚且つ、半導体基板10の外周部Pexに第2種類のドーパントを選択的に注入する。
図9は、第4の実施形態による半導体装置の製造方法に従って形成された被研磨膜20に含まれるドーパントの濃度を示すグラフである。尚、縦軸は、ドーパントの濃度を示し、横軸は、被研磨膜20の表面からの深さを示す。
図10は、第5の実施形態による半導体装置の製造方法を示す平面図である。図10に示す半導体基板10の面内において、リソグラフィ工程におけるショットが実線の枠SHdまたはSHndで示されている。枠内に×が示されているショット領域SHndは、パターン(ダミーパターン)が形成されていない領域である。枠内に×が示されていないショット領域SHdは、パターン(またはダミーパターン)が形成されている領域である。また、半導体基板10の太枠線B内に製品チップCHが形成される。製品チップCHは破線の枠で示されている。太線枠Bの外側の半導体基板10には、製品チップCHは形成されない。従って、太線枠Bの外側のショット領域SHdには、ダミーパターンが形成される。太線枠Bの外側のうちショット領域SHndには、パターン(ダミーパターン)は形成されない。
Claims (4)
- CまたはSiイオンを不純物として被研磨膜の外周部に局所的に注入することにより、該外周部においてCまたはSiイオンの不純物濃度をF、B、PまたはNイオンの不純物濃度よりも大きくして該被研磨膜の表面を改質し、
CまたはSiイオンの注入後、前記被研磨膜の研磨前に、前記被研磨膜を熱処理し、
改質後の前記被研磨膜の表面を、CMP法を用いて研磨することを具備する半導体装置の製造方法。 - 前記熱処理後、前記研磨前に、F、B、PまたはNイオンを不純物として前記被研磨膜の表面の中心部へ局所的に注入することにより、該中心部においてF、B、PまたはNイオンの不純物濃度をCまたはSiイオンの不純物濃度よりも大きくして該被研磨膜の表面を改質することをさらに具備する、請求項1に記載の半導体装置の製造方法。
- 前記イオンは、前記被研磨膜の深さ方向の濃度プロファイルが複数のピークを有するように注入されることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記被研磨膜の熱処理は、900℃以上の温度で実行される、請求項1から請求項3のいずれか一項に記載の半導体装置の製造方法。
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JP2014152285A JP6196589B2 (ja) | 2014-07-25 | 2014-07-25 | 半導体装置の製造方法および半導体製造装置 |
US14/643,218 US10008390B2 (en) | 2014-07-25 | 2015-03-10 | Manufacturing method of semiconductor device and semiconductor manufacturing apparatus |
US15/992,223 US20180277388A1 (en) | 2014-07-25 | 2018-05-30 | Manufacturing method of semiconductor device and semiconductor manufacturing apparatus |
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JP2014152285A JP6196589B2 (ja) | 2014-07-25 | 2014-07-25 | 半導体装置の製造方法および半導体製造装置 |
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JP2017155935A Division JP2017228785A (ja) | 2017-08-10 | 2017-08-10 | 半導体装置の製造方法および半導体製造装置 |
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JP2016031947A5 JP2016031947A5 (ja) | 2016-04-14 |
JP6196589B2 true JP6196589B2 (ja) | 2017-09-13 |
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Cited By (1)
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US10777424B2 (en) | 2018-02-27 | 2020-09-15 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
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JP2626502B2 (ja) * | 1993-09-14 | 1997-07-02 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP3514908B2 (ja) * | 1995-11-13 | 2004-04-05 | 株式会社東芝 | 研磨剤 |
JPH09162144A (ja) | 1995-12-05 | 1997-06-20 | Toshiba Corp | 半導体装置の製造方法 |
JP3147089B2 (ja) | 1998-06-23 | 2001-03-19 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2001044201A (ja) | 1999-07-29 | 2001-02-16 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
DE10056872C1 (de) * | 2000-11-16 | 2002-06-13 | Advanced Micro Devices Inc | Implantationsüberwachung unter Anwendung mehrerer Implantations- und Temperschritte |
US6713385B1 (en) * | 2002-10-31 | 2004-03-30 | Intel Corporation | Implanting ions in shallow trench isolation structures |
JP2004207385A (ja) * | 2002-12-24 | 2004-07-22 | Rohm Co Ltd | マスク、その製造方法およびこれを用いた半導体装置の製造方法 |
JP2007002268A (ja) | 2005-06-21 | 2007-01-11 | Plasma Ion Assist Co Ltd | 研磨用部材の表面処理方法及びその物品 |
JP2008016692A (ja) * | 2006-07-07 | 2008-01-24 | Fujifilm Corp | 半導体装置の製造方法 |
US8153513B2 (en) * | 2006-07-25 | 2012-04-10 | Silicon Genesis Corporation | Method and system for continuous large-area scanning implantation process |
US7767583B2 (en) * | 2008-03-04 | 2010-08-03 | Varian Semiconductor Equipment Associates, Inc. | Method to improve uniformity of chemical mechanical polishing planarization |
JP2011138826A (ja) * | 2009-12-25 | 2011-07-14 | Nitta Haas Inc | 半導体デバイス用基板およびsoi基板 |
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2014
- 2014-07-25 JP JP2014152285A patent/JP6196589B2/ja active Active
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- 2015-03-10 US US14/643,218 patent/US10008390B2/en active Active
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Publication number | Priority date | Publication date | Assignee | Title |
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US10777424B2 (en) | 2018-02-27 | 2020-09-15 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
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US20180277388A1 (en) | 2018-09-27 |
US20160027660A1 (en) | 2016-01-28 |
JP2016031947A (ja) | 2016-03-07 |
US10008390B2 (en) | 2018-06-26 |
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