JP6168153B2 - 半導体装置 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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Description
また、特には、前記第1封止層が、前記半導体素子の動作時に、前記半導体素子の最大動作温度から25℃以内となる領域を少なくとも封止することが好ましい。
また、特には、前記第2封止層が、3mm以下の厚みであることが好ましい。
また、特には、前記第1封止層が、前記半導体素子の動作時に、前記半導体素子の最大動作温度から25℃以内となる領域を少なくとも封止し、前記第3封止層が、3mm以下の厚みであることが好ましい。
本発明は、第1実施形態によれば、半導体装置であって、半導体素子と、前記半導体素子の一方の面に接合された絶縁基板と、前記半導体素子の他方の面に接合された外部回路との接続用プリント基板とを含む部材を、封止材で封止してなる成形体を備え、エポキシ樹脂主剤と、硬化剤と、平均粒経が1〜100nmの無機充填材とを含んでなるナノコンポジット樹脂である第1の封止材が前記半導体素子を被覆して、前記半導体素子に近接する領域に設けられる第1封止層を構成し、熱硬化性樹脂もしくは熱可塑性樹脂あるいはそれらの混合物からなる第2の封止材が、前記第1封止層を被覆し、かつ前記成形体の外表面を形成する第2封止層を構成する、二層封止構造の封止部を備える。
本発明は、第2実施形態によれば、半導体装置であって、半導体素子と、前記半導体素子の一方の面に接合された絶縁基板と、前記半導体素子の他方の面に接合された外部回路との接続用プリント基板とを含む部材を、封止材で封止してなる成形体を備え、熱硬化性樹脂または熱可塑性樹脂である第2の封止材が、前記半導体素子を被覆する第1封止層を構成し、ナノコンポジット樹脂である第1の封止材が、前記第1封止層を被覆し、かつ前記成形体の外表面の少なくとも一部に面して、少なくとも300μmの厚みで設けられる第2封止層を構成することを特徴とする。
本発明は、第3実施形態によれば、半導体装置であって、半導体素子と、前記半導体素子の一方の面に接合された絶縁基板と、前記半導体素子の他方の面に接合された外部回路との接続用プリント基板とを含む部材を、封止材で封止してなる成形体を備え、ナノコンポジット樹脂である第1の封止材が、前記半導体素子を被覆して前記半導体素子に近接する領域に設けられる第1封止層を構成し、熱硬化性樹脂または熱可塑性樹脂である第2の封止材が、前記第1封止層を被覆する第2封止層を構成し、ナノコンポジット樹脂である第1の封止材が、前記第2の封止材をさらに被覆して、かつ、前記成形体の外表面の少なくとも一部に面して、少なくとも300μmの厚みで設けられる第3封止層を構成することを特徴とする。
2 第1銅ブロック
3 第2銅ブロック
4 絶縁基板
5 導電接合層a
6 SiC半導体素子
7 導電接合層b
8 インプラントピン
9 インプラント方式プリント基板
11 樹脂
12 取り付け金具
13 ナノコンポジット樹脂
100 半導体モジュール成形構造体
200 半導体モジュール成形構造体
300 半導体モジュール成形構造体
Claims (6)
- 半導体素子と、前記半導体素子の一方の面に接合された絶縁基板と、前記半導体素子の他方の面に接合された外部回路との接続用プリント基板とを含む部材を、封止材で封止してなる成形体を備える半導体装置であって、
前記封止材が、
エポキシ樹脂主剤と、硬化剤と、平均粒経が1〜100nmの無機充填材と、難燃剤とを含んでなるナノコンポジット樹脂である第1の封止材と、
熱硬化性樹脂もしくは熱可塑性樹脂あるいはそれらの混合物からなる第2の封止材とを含んでなり、
前記第1の封止材が、前記半導体素子を被覆して前記半導体素子に近接する領域に設けられる第1封止層を構成し、
前記第2の封止材が、前記第1封止層を被覆し、かつ前記成形体の外表面を形成する第2封止層を構成する、半導体装置。 - 前記第1封止層が、前記半導体素子の動作時に、前記半導体素子の最大動作温度から25℃以内となる領域を少なくとも封止する、請求項1に記載の半導体装置。
- 半導体素子と、前記半導体素子の一方の面に接合された絶縁基板と、前記半導体素子の他方の面に接合された外部回路との接続用プリント基板とを含む部材を、封止材で封止してなる成形体を備える半導体装置であって、
前記封止材が、
エポキシ樹脂主剤と、硬化剤と、平均粒経が1〜100nmの無機充填材と、難燃剤とを含んでなるナノコンポジット樹脂である第1の封止材と、
熱硬化性樹脂もしくは熱可塑性樹脂あるいはそれらの混合物からなる第2の封止材と
を含んでなり、
前記第1の封止材が、前記半導体素子を被覆して前記半導体素子に近接する領域に設けられる第1封止層を構成し、
前記第2の封止材が、前記第1の封止材を被覆する第2封止層を構成し、
前記第1の封止材が、前記第2封止層をさらに被覆し、かつ前記成形体の外表面の少なくとも一部に面して、少なくとも300μmの厚みで設けられる第3封止層を構成する、
半導体装置。 - 前記第1封止層が、前記半導体素子の動作時に、前記半導体素子の最大動作温度から25℃以内となる領域を少なくとも封止し、
前記第3封止層が、3mm以下の厚みである、請求項3に記載の半導体装置。 - 前記無機充填材が、溶融シリカもしくは破砕シリカの少なくとも一方を含む、請求項1〜4のいずれか1項に記載の半導体装置。
- 前記半導体素子が、SiC半導体素子である、請求項1〜5のいずれか1項に記載の半導体装置。
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Application Number | Priority Date | Filing Date | Title |
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JP2013190787 | 2013-09-13 | ||
JP2013190787 | 2013-09-13 | ||
PCT/JP2014/069813 WO2015037349A1 (ja) | 2013-09-13 | 2014-07-28 | 半導体装置 |
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JPWO2015037349A1 JPWO2015037349A1 (ja) | 2017-03-02 |
JP6168153B2 true JP6168153B2 (ja) | 2017-07-26 |
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US (1) | US9443779B2 (ja) |
JP (1) | JP6168153B2 (ja) |
CN (1) | CN105190872B (ja) |
DE (1) | DE112014000851T5 (ja) |
WO (1) | WO2015037349A1 (ja) |
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JP6369228B2 (ja) * | 2014-08-29 | 2018-08-08 | 富士電機株式会社 | 半導体装置 |
WO2017086913A1 (en) * | 2015-11-16 | 2017-05-26 | Hewlett-Packard Development Company, L.P. | Circuit package |
US10262914B2 (en) | 2015-12-25 | 2019-04-16 | Sumitomo Bakelite Co., Ltd. | Resin composition for encapsulation, and semiconductor device |
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DE112011103323T5 (de) | 2010-10-01 | 2013-07-11 | Fuji Electric Co., Ltd. | Kunststoffzusammensetzung |
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JP5807348B2 (ja) * | 2011-03-10 | 2015-11-10 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP5857464B2 (ja) | 2011-06-16 | 2016-02-10 | 富士電機株式会社 | パワー半導体モジュールおよびその製造方法 |
JP5999468B2 (ja) * | 2011-10-18 | 2016-09-28 | 富士電機株式会社 | ポリマーナノコンポジット樹脂組成物 |
JP5966414B2 (ja) * | 2012-02-17 | 2016-08-10 | 富士電機株式会社 | パワー半導体モジュール |
JP6167535B2 (ja) | 2013-01-30 | 2017-07-26 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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WO2015037349A1 (ja) | 2015-03-19 |
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