JP6154995B2 - 半導体装置及び配線基板、並びにそれらの製造方法 - Google Patents

半導体装置及び配線基板、並びにそれらの製造方法 Download PDF

Info

Publication number
JP6154995B2
JP6154995B2 JP2012138474A JP2012138474A JP6154995B2 JP 6154995 B2 JP6154995 B2 JP 6154995B2 JP 2012138474 A JP2012138474 A JP 2012138474A JP 2012138474 A JP2012138474 A JP 2012138474A JP 6154995 B2 JP6154995 B2 JP 6154995B2
Authority
JP
Japan
Prior art keywords
forming
pedestal
opening
columnar
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012138474A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014003201A (ja
JP2014003201A5 (enExample
Inventor
洋弘 町田
洋弘 町田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012138474A priority Critical patent/JP6154995B2/ja
Priority to US13/920,336 priority patent/US9082672B2/en
Publication of JP2014003201A publication Critical patent/JP2014003201A/ja
Publication of JP2014003201A5 publication Critical patent/JP2014003201A5/ja
Application granted granted Critical
Publication of JP6154995B2 publication Critical patent/JP6154995B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Ceramic Engineering (AREA)
JP2012138474A 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法 Active JP6154995B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012138474A JP6154995B2 (ja) 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法
US13/920,336 US9082672B2 (en) 2012-06-20 2013-06-18 Semiconductor device and method of manufacturing the same, and wiring substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012138474A JP6154995B2 (ja) 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法

Publications (3)

Publication Number Publication Date
JP2014003201A JP2014003201A (ja) 2014-01-09
JP2014003201A5 JP2014003201A5 (enExample) 2015-07-23
JP6154995B2 true JP6154995B2 (ja) 2017-06-28

Family

ID=49773731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012138474A Active JP6154995B2 (ja) 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法

Country Status (2)

Country Link
US (1) US9082672B2 (enExample)
JP (1) JP6154995B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7117615B2 (ja) * 2017-12-08 2022-08-15 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法
JP7357243B2 (ja) * 2019-04-18 2023-10-06 パナソニックＩｐマネジメント株式会社 半導体装置、半導体装置の実装構造、及び半導体装置の製造方法
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3015436B2 (ja) * 1990-09-25 2000-03-06 株式会社東芝 半導体装置およびその接続方法
SG71734A1 (en) * 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
JP4403631B2 (ja) * 2000-04-24 2010-01-27 ソニー株式会社 チップ状電子部品の製造方法、並びにその製造に用いる擬似ウエーハの製造方法
US6940178B2 (en) * 2001-02-27 2005-09-06 Chippac, Inc. Self-coplanarity bumping shape for flip chip
JP3851517B2 (ja) * 2001-04-18 2006-11-29 カシオマイクロニクス株式会社 半導体装置およびその製造方法並びにその接合構造
JP2004200247A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 端子、端子の形成方法、半導体チップ、半導体実装基板、電子デバイスおよび電子機器
JP2005116632A (ja) * 2003-10-03 2005-04-28 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2007073919A (ja) * 2005-09-06 2007-03-22 Tanemasa Asano 突起電極の製造方法およびそれに用いられるベーク装置ならびに電子装置
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
JP5865630B2 (ja) * 2011-08-23 2016-02-17 京セラ株式会社 電極構造、半導体素子、半導体装置、サーマルヘッドおよびサーマルプリンタ

Also Published As

Publication number Publication date
JP2014003201A (ja) 2014-01-09
US9082672B2 (en) 2015-07-14
US20130341788A1 (en) 2013-12-26

Similar Documents

Publication Publication Date Title
CN101183668B (zh) 电解电镀形成突起电极的半导体装置及其制造方法
KR101867893B1 (ko) 배선 기판 및 그 제조 방법
KR101708535B1 (ko) 집적 회로 장치 및 그 제조방법
JP2002076047A (ja) バンプの形成方法、半導体装置及びその製造方法、回路基板並びに電子機器
US7132358B2 (en) Method of forming solder bump with reduced surface defects
CN108538801B (zh) 半导体衬底及半导体封装装置，以及用于形成半导体衬底的方法
JP2010238702A (ja) 半導体パッケージの製造方法および半導体パッケージ
JP2010103187A (ja) プリント配線板及びその製造方法
TW201511203A (zh) 半導體裝置
JP2003203940A (ja) 半導体チップ及び配線基板並びにこれらの製造方法、半導体ウエハ、半導体装置、回路基板並びに電子機器
JP6619294B2 (ja) 配線基板及びその製造方法と電子部品装置
JP2002203869A (ja) バンプの形成方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP6154995B2 (ja) 半導体装置及び配線基板、並びにそれらの製造方法
JP7700986B2 (ja) 配線基板及びその製造方法
US10643934B2 (en) Wiring substrate and electronic component device
US9524944B2 (en) Method for fabricating package structure
JP7711870B2 (ja) 配線基板及びその製造方法
JP5247998B2 (ja) 半導体装置の製造方法
JP4949790B2 (ja) 半導体装置の製造方法
JP2001148393A (ja) バンプの形成方法、半導体装置及びその製造方法、回路基板並びに電子機器
US11749596B2 (en) Wiring substrate
JP5022963B2 (ja) 突起電極の構造、素子搭載用基板およびその製造方法、半導体モジュール、ならびに携帯機器
JP2002299361A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2013004921A (ja) 突起電極の製造方法
JP2004281614A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150608

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150608

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160304

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160405

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160603

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170516

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170605

R150 Certificate of patent or registration of utility model

Ref document number: 6154995

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150