JP6154995B2 - 半導体装置及び配線基板、並びにそれらの製造方法 - Google Patents

半導体装置及び配線基板、並びにそれらの製造方法 Download PDF

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JP6154995B2
JP6154995B2 JP2012138474A JP2012138474A JP6154995B2 JP 6154995 B2 JP6154995 B2 JP 6154995B2 JP 2012138474 A JP2012138474 A JP 2012138474A JP 2012138474 A JP2012138474 A JP 2012138474A JP 6154995 B2 JP6154995 B2 JP 6154995B2
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forming
pedestal
opening
columnar
metal layer
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JP2014003201A (ja
JP2014003201A5 (enExample
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洋弘 町田
洋弘 町田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2012138474A priority Critical patent/JP6154995B2/ja
Priority to US13/920,336 priority patent/US9082672B2/en
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2012138474A 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法 Active JP6154995B2 (ja)

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Application Number Priority Date Filing Date Title
JP2012138474A JP6154995B2 (ja) 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法
US13/920,336 US9082672B2 (en) 2012-06-20 2013-06-18 Semiconductor device and method of manufacturing the same, and wiring substrate and method of manufacturing the same

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JP2012138474A JP6154995B2 (ja) 2012-06-20 2012-06-20 半導体装置及び配線基板、並びにそれらの製造方法

Publications (3)

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JP2014003201A JP2014003201A (ja) 2014-01-09
JP2014003201A5 JP2014003201A5 (enExample) 2015-07-23
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US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
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