JP6136061B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6136061B2 JP6136061B2 JP2012272489A JP2012272489A JP6136061B2 JP 6136061 B2 JP6136061 B2 JP 6136061B2 JP 2012272489 A JP2012272489 A JP 2012272489A JP 2012272489 A JP2012272489 A JP 2012272489A JP 6136061 B2 JP6136061 B2 JP 6136061B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
Description
図1は、本発明の実施の形態に係る半導体装置の断面図である。この半導体装置は、多層基板10を備えている。多層基板10は、基板10a、基板10b、及び基板10cが重ねられたものである。多層基板10は樹脂又はセラミックで形成されている。
Claims (2)
- 半導体装置であって、
多層基板と、
前記多層基板の上面に固定された半導体デバイスと、
前記半導体デバイスと電気的に接続され、前記多層基板内に前記多層基板の下面に至るように形成された基板内ビアと、
前記多層基板の下面の一部に形成された第1金属パターンと、
前記基板内ビアの下端に接するように形成された第2金属パターンと、
前記多層基板の下面に、前記第1金属パターン及び前記第2金属パターンを覆うように形成された前記多層基板よりも誘電率が高い誘電体と、
前記誘電体内に、上端で前記第1金属パターンと接続され、前記誘電体の下面に至るように形成された第1誘電体内ビアと、
前記誘電体内に、上端で前記第2金属パターンと接続され、前記誘電体の下面に至るように形成された第2誘電体内ビアと、
前記第1誘電体内ビアの下端と直接接続された接地パターンと、
前記第2誘電体内ビアの下端と直接接続され、電源が供給される裏面電極と、を備え、
前記接地パターン及び前記裏面電極は、前記半導体装置の裏面において露出し、
前記裏面電極の一部の直上には、前記誘電体を介して前記第1金属パターンの一部が配置され、前記裏面電極、前記誘電体、及び前記第1金属パターンでバイパスコンデンサを形成し、
前記バイパスコンデンサは、前記第1金属パターン、前記第1誘電体内ビア、及び前記接地パターンを通じて接地されることを特徴とする半導体装置。 - 前記誘電体の比誘電率は1000以上であることを特徴とする請求項1に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012272489A JP6136061B2 (ja) | 2012-12-13 | 2012-12-13 | 半導体装置 |
US13/975,505 US8796817B2 (en) | 2012-12-13 | 2013-08-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012272489A JP6136061B2 (ja) | 2012-12-13 | 2012-12-13 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2014120519A JP2014120519A (ja) | 2014-06-30 |
JP6136061B2 true JP6136061B2 (ja) | 2017-05-31 |
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JP2012272489A Active JP6136061B2 (ja) | 2012-12-13 | 2012-12-13 | 半導体装置 |
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Country | Link |
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US (1) | US8796817B2 (ja) |
JP (1) | JP6136061B2 (ja) |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06302760A (ja) | 1993-04-13 | 1994-10-28 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP3499255B2 (ja) * | 1993-05-21 | 2004-02-23 | 株式会社半導体エネルギー研究所 | 複合集積回路部品の作製方法 |
JPH0730257A (ja) * | 1993-07-13 | 1995-01-31 | Fujitsu Ltd | コンデンサ内蔵薄膜多層配線板 |
JP3443436B2 (ja) * | 1993-08-31 | 2003-09-02 | 京セラ株式会社 | 容量内蔵型多層回路基板 |
JPH0935997A (ja) * | 1995-07-24 | 1997-02-07 | Mitsubishi Materials Corp | 薄膜コンデンサ内蔵型モジュール |
JPH1093246A (ja) * | 1996-09-18 | 1998-04-10 | Kyocera Corp | 多層配線基板 |
JP3976954B2 (ja) * | 1999-08-27 | 2007-09-19 | 新光電気工業株式会社 | 多層配線基板の製造方法及び半導体装置 |
US6470545B1 (en) * | 1999-09-15 | 2002-10-29 | National Semiconductor Corporation | Method of making an embedded green multi-layer ceramic chip capacitor in a low-temperature co-fired ceramic (LTCC) substrate |
JP2001185442A (ja) * | 1999-12-27 | 2001-07-06 | Murata Mfg Co Ltd | 積層コンデンサ、デカップリングコンデンサの接続構造および配線基板 |
JP2002008942A (ja) * | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | コンデンサ装置、コンデンサ装置の製造方法及びコンデンサ装置が実装されたモジュール |
JP3669255B2 (ja) * | 2000-09-19 | 2005-07-06 | 株式会社村田製作所 | セラミック多層基板の製造方法および未焼成セラミック積層体 |
JP2002252297A (ja) * | 2001-02-23 | 2002-09-06 | Hitachi Ltd | 多層回路基板を用いた電子回路装置 |
JP2003086950A (ja) | 2001-07-06 | 2003-03-20 | Matsushita Electric Works Ltd | プリント配線板 |
JP3967108B2 (ja) * | 2001-10-26 | 2007-08-29 | 富士通株式会社 | 半導体装置およびその製造方法 |
KR100598275B1 (ko) * | 2004-09-15 | 2006-07-10 | 삼성전기주식회사 | 수동소자 내장형 인쇄회로기판 및 그 제조 방법 |
CN1906986B (zh) * | 2004-10-29 | 2010-05-12 | 株式会社村田制作所 | 内装片状电子元器件的多层基板及其制造方法 |
JP4967241B2 (ja) | 2005-02-25 | 2012-07-04 | パナソニック株式会社 | コンデンサ内蔵配線基板及びその製造方法と電子機器 |
KR100923895B1 (ko) * | 2005-06-13 | 2009-10-28 | 이비덴 가부시키가이샤 | 프린트 배선판 |
JPWO2009028596A1 (ja) * | 2007-08-30 | 2010-12-02 | 日本電気株式会社 | 受動素子内蔵基板、製造方法、及び半導体装置 |
-
2012
- 2012-12-13 JP JP2012272489A patent/JP6136061B2/ja active Active
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2013
- 2013-08-26 US US13/975,505 patent/US8796817B2/en active Active
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Publication number | Publication date |
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US20140167282A1 (en) | 2014-06-19 |
JP2014120519A (ja) | 2014-06-30 |
US8796817B2 (en) | 2014-08-05 |
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