JP6092649B2 - 演算装置、アレイ型演算装置およびその制御方法、情報処理システム - Google Patents
演算装置、アレイ型演算装置およびその制御方法、情報処理システム Download PDFInfo
- Publication number
- JP6092649B2 JP6092649B2 JP2013028344A JP2013028344A JP6092649B2 JP 6092649 B2 JP6092649 B2 JP 6092649B2 JP 2013028344 A JP2013028344 A JP 2013028344A JP 2013028344 A JP2013028344 A JP 2013028344A JP 6092649 B2 JP6092649 B2 JP 6092649B2
- Authority
- JP
- Japan
- Prior art keywords
- configuration information
- unit
- array type
- control
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/442—Shutdown
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013028344A JP6092649B2 (ja) | 2013-02-15 | 2013-02-15 | 演算装置、アレイ型演算装置およびその制御方法、情報処理システム |
| US14/178,479 US9916166B2 (en) | 2013-02-15 | 2014-02-12 | Power supply control for a processing device, array-type processing device,and information processing system, and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013028344A JP6092649B2 (ja) | 2013-02-15 | 2013-02-15 | 演算装置、アレイ型演算装置およびその制御方法、情報処理システム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014157508A JP2014157508A (ja) | 2014-08-28 |
| JP2014157508A5 JP2014157508A5 (enExample) | 2016-02-25 |
| JP6092649B2 true JP6092649B2 (ja) | 2017-03-08 |
Family
ID=51352168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013028344A Expired - Fee Related JP6092649B2 (ja) | 2013-02-15 | 2013-02-15 | 演算装置、アレイ型演算装置およびその制御方法、情報処理システム |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9916166B2 (enExample) |
| JP (1) | JP6092649B2 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10075392B1 (en) | 2017-03-02 | 2018-09-11 | Micron Technology, Inc. | Methods and apparatuses for processing multiple communications signals with a single integrated circuit chip |
| US11055657B2 (en) * | 2017-03-02 | 2021-07-06 | Micron Technology, Inc. | Methods and apparatuses for determining real-time location information of RFID devices |
| CN107807901A (zh) * | 2017-09-14 | 2018-03-16 | 武汉科技大学 | 一种可扩展的可重构多核处理器连接方法 |
| US11188497B2 (en) | 2018-11-21 | 2021-11-30 | SambaNova Systems, Inc. | Configuration unload of a reconfigurable data processor |
| US10831507B2 (en) * | 2018-11-21 | 2020-11-10 | SambaNova Systems, Inc. | Configuration load of a reconfigurable data processor |
| US10698853B1 (en) | 2019-01-03 | 2020-06-30 | SambaNova Systems, Inc. | Virtualization of a reconfigurable data processor |
| US10768899B2 (en) | 2019-01-29 | 2020-09-08 | SambaNova Systems, Inc. | Matrix normal/transpose read and a reconfigurable data processor including same |
| JP7325210B2 (ja) * | 2019-04-08 | 2023-08-14 | キヤノン株式会社 | 情報処理装置及びその制御方法 |
| US11386038B2 (en) | 2019-05-09 | 2022-07-12 | SambaNova Systems, Inc. | Control flow barrier and reconfigurable data processor |
| US11055141B2 (en) | 2019-07-08 | 2021-07-06 | SambaNova Systems, Inc. | Quiesce reconfigurable data processor |
| BR112023023650A2 (pt) | 2020-04-04 | 2024-01-30 | Janux Therapeutics Inc | Composições e métodos relacionados a anticorpos ativados por tumores direcionados a egfr e antígenos de células efetoras |
| US11809908B2 (en) | 2020-07-07 | 2023-11-07 | SambaNova Systems, Inc. | Runtime virtualization of reconfigurable data flow resources |
| US11782729B2 (en) | 2020-08-18 | 2023-10-10 | SambaNova Systems, Inc. | Runtime patching of configuration files |
| US11556494B1 (en) | 2021-07-16 | 2023-01-17 | SambaNova Systems, Inc. | Defect repair for a reconfigurable data processor for homogeneous subarrays |
| US11327771B1 (en) | 2021-07-16 | 2022-05-10 | SambaNova Systems, Inc. | Defect repair circuits for a reconfigurable data processor |
| US11409540B1 (en) | 2021-07-16 | 2022-08-09 | SambaNova Systems, Inc. | Routing circuits for defect repair for a reconfigurable data processor |
| US11487694B1 (en) | 2021-12-17 | 2022-11-01 | SambaNova Systems, Inc. | Hot-plug events in a pool of reconfigurable data flow resources |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7539878B2 (en) * | 2001-09-19 | 2009-05-26 | Freescale Semiconductor, Inc. | CPU powerdown method and apparatus therefor |
| JP2005011166A (ja) * | 2003-06-20 | 2005-01-13 | Renesas Technology Corp | 情報処理装置 |
| US7183825B2 (en) * | 2004-04-06 | 2007-02-27 | Freescale Semiconductor, Inc. | State retention within a data processing system |
| JP3810419B2 (ja) * | 2004-12-07 | 2006-08-16 | 松下電器産業株式会社 | 再構成可能な信号処理プロセッサ |
| US7257723B2 (en) * | 2005-01-07 | 2007-08-14 | Atheros Communications, Inc. | Reducing power consumption in embedded systems by controlling voltage based on system state and partition designation |
| US7659746B2 (en) * | 2005-02-14 | 2010-02-09 | Qualcomm, Incorporated | Distributed supply current switch circuits for enabling individual power domains |
| JP2008097463A (ja) * | 2006-10-13 | 2008-04-24 | Canon Inc | データ処理装置 |
| KR101053903B1 (ko) * | 2007-10-19 | 2011-08-04 | 삼성전자주식회사 | 네트워크온칩에서 전압 및 주파수 제어 장치 및 방법 |
| US7830039B2 (en) * | 2007-12-28 | 2010-11-09 | Sandisk Corporation | Systems and circuits with multirange and localized detection of valid power |
| US8140830B2 (en) * | 2008-05-22 | 2012-03-20 | International Business Machines Corporation | Structural power reduction in multithreaded processor |
| JP5431003B2 (ja) | 2009-04-03 | 2014-03-05 | スパンション エルエルシー | リコンフィギュラブル回路及びリコンフィギュラブル回路システム |
| US8468373B2 (en) * | 2011-01-14 | 2013-06-18 | Apple Inc. | Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state |
| US9229524B2 (en) * | 2012-06-27 | 2016-01-05 | Intel Corporation | Performing local power gating in a processor |
| US9405357B2 (en) * | 2013-04-01 | 2016-08-02 | Advanced Micro Devices, Inc. | Distribution of power gating controls for hierarchical power domains |
-
2013
- 2013-02-15 JP JP2013028344A patent/JP6092649B2/ja not_active Expired - Fee Related
-
2014
- 2014-02-12 US US14/178,479 patent/US9916166B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9916166B2 (en) | 2018-03-13 |
| JP2014157508A (ja) | 2014-08-28 |
| US20140237227A1 (en) | 2014-08-21 |
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