JP6092427B2 - ｎウェル切替回路 - Google Patents

ｎウェル切替回路 Download PDF

Info

Publication number
JP6092427B2
JP6092427B2 JP2015552832A JP2015552832A JP6092427B2 JP 6092427 B2 JP6092427 B2 JP 6092427B2 JP 2015552832 A JP2015552832 A JP 2015552832A JP 2015552832 A JP2015552832 A JP 2015552832A JP 6092427 B2 JP6092427 B2 JP 6092427B2
Authority
JP
Japan
Prior art keywords
well
pmos transistor
voltage
switching circuit
switched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015552832A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016511933A5 (enExample
JP2016511933A (ja
Inventor
タージオグル、イージン
ウビーグハラ、グレゴリー・アメリアダ
ユン、セイ・スン
ガニサン、バラチャンダー
コタ、アニル・チョーダリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2016511933A publication Critical patent/JP2016511933A/ja
Publication of JP2016511933A5 publication Critical patent/JP2016511933A5/ja
Application granted granted Critical
Publication of JP6092427B2 publication Critical patent/JP6092427B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0072—Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2015552832A 2013-01-16 2014-01-10 ｎウェル切替回路 Expired - Fee Related JP6092427B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/742,964 US8787096B1 (en) 2013-01-16 2013-01-16 N-well switching circuit
US13/742,964 2013-01-16
PCT/US2014/011138 WO2014113295A1 (en) 2013-01-16 2014-01-10 N-well switching circuit

Publications (3)

Publication Number Publication Date
JP2016511933A JP2016511933A (ja) 2016-04-21
JP2016511933A5 JP2016511933A5 (enExample) 2017-01-19
JP6092427B2 true JP6092427B2 (ja) 2017-03-08

Family

ID=50031588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015552832A Expired - Fee Related JP6092427B2 (ja) 2013-01-16 2014-01-10 ｎウェル切替回路

Country Status (6)

Country Link
US (2) US8787096B1 (enExample)
EP (1) EP2946474B1 (enExample)
JP (1) JP6092427B2 (enExample)
KR (1) KR101557812B1 (enExample)
CN (1) CN104937848B (enExample)
WO (1) WO2014113295A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8787096B1 (en) 2013-01-16 2014-07-22 Qualcomm Incorporated N-well switching circuit
US9082498B2 (en) * 2013-08-08 2015-07-14 Qualcomm Incorporated N-well switching circuit
TWI739734B (zh) 2015-02-23 2021-09-21 紐西蘭商藍瑟科技紐西蘭有限公司 用於將甲烷轉化為產物之重組產醋酸細菌
CN105049029B (zh) * 2015-07-06 2018-05-04 上海巨微集成电路有限公司 一种pmos管衬底切换电路
JP6905518B2 (ja) 2015-10-13 2021-07-21 ランザテク・ニュージーランド・リミテッド エネルギー発生発酵経路を含む遺伝子操作細菌
KR20180127632A (ko) 2015-12-03 2018-11-29 란자테크 뉴질랜드 리미티드 가스 발효 아세토젠에서의 효율을 개선하기 위한 아르기닌 보충
KR20180118651A (ko) 2016-02-01 2018-10-31 란자테크 뉴질랜드 리미티드 통합형 발효 및 전해 공정
EP3420089B1 (en) 2016-02-26 2021-12-29 LanzaTech NZ, Inc. Crispr/cas systems for c-1 fixing bacteria
US9570192B1 (en) 2016-03-04 2017-02-14 Qualcomm Incorporated System and method for reducing programming voltage stress on memory cell devices
AU2019218389B2 (en) 2018-02-12 2024-09-05 Lanzatech, Inc. A process for improving carbon conversion efficiency
AU2019257224B2 (en) 2018-04-20 2024-12-19 Lanzatech, Inc. Intermittent electrolysis streams
CN113225056A (zh) * 2021-05-21 2021-08-06 上海韦尔半导体股份有限公司 一种控制电路、电路控制方法及电子产品
US12212315B1 (en) * 2023-01-04 2025-01-28 Cadence Design Systems, Inc. Interface device

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670668A (en) 1985-05-09 1987-06-02 Advanced Micro Devices, Inc. Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
JP3264622B2 (ja) 1996-07-16 2002-03-11 株式会社東芝 半導体装置
US5844425A (en) 1996-07-19 1998-12-01 Quality Semiconductor, Inc. CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations
JP4105833B2 (ja) * 1998-09-09 2008-06-25 株式会社ルネサステクノロジ 半導体集積回路装置
TW453032B (en) * 1998-09-09 2001-09-01 Hitachi Ltd Semiconductor integrated circuit apparatus
US6452858B1 (en) * 1999-11-05 2002-09-17 Hitachi, Ltd. Semiconductor device
US6377112B1 (en) 2000-12-05 2002-04-23 Semiconductor Components Industries Llc Circuit and method for PMOS device N-well bias control
US6573134B2 (en) * 2001-03-27 2003-06-03 Sharp Laboratories Of America, Inc. Dual metal gate CMOS devices and method for making the same
US7218151B1 (en) * 2002-06-28 2007-05-15 University Of Rochester Domino logic with variable threshold voltage keeper
US6882188B1 (en) * 2003-09-30 2005-04-19 Faraday Technology Corp. Input/output buffer
US7038274B2 (en) * 2003-11-13 2006-05-02 Volterra Semiconductor Corporation Switching regulator with high-side p-type device
US7046493B2 (en) * 2003-12-12 2006-05-16 Faraday Technology Corp. Input/output buffer protection circuit
KR100728950B1 (ko) * 2004-03-11 2007-06-15 주식회사 하이닉스반도체 내부전압 발생장치
FR2894373B1 (fr) * 2005-12-07 2008-01-04 Atmel Corp Cellule anti-fusible autonome
US7355437B2 (en) * 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7330049B2 (en) * 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
TWI451697B (zh) * 2006-05-03 2014-09-01 Synopsys Inc 極低功率類比補償電路
US7863962B2 (en) * 2008-04-17 2011-01-04 National Semiconductor Corporation High voltage CMOS output buffer constructed from low voltage CMOS transistors
US7800179B2 (en) * 2009-02-04 2010-09-21 Fairchild Semiconductor Corporation High speed, low power consumption, isolated analog CMOS unit
CN101997305B (zh) 2009-08-26 2013-04-10 安凯(广州)微电子技术有限公司 一种反向电压保护电路及功率管装置
US8787096B1 (en) 2013-01-16 2014-07-22 Qualcomm Incorporated N-well switching circuit

Also Published As

Publication number Publication date
KR101557812B1 (ko) 2015-10-06
CN104937848B (zh) 2017-12-05
WO2014113295A1 (en) 2014-07-24
US20140198588A1 (en) 2014-07-17
EP2946474B1 (en) 2016-07-27
US20140369152A1 (en) 2014-12-18
US8787096B1 (en) 2014-07-22
CN104937848A (zh) 2015-09-23
EP2946474A1 (en) 2015-11-25
US9252765B2 (en) 2016-02-02
KR20150097815A (ko) 2015-08-26
JP2016511933A (ja) 2016-04-21

Similar Documents

Publication Publication Date Title
JP6092427B2 (ja) ｎウェル切替回路
JP2016511933A5 (enExample)
US8184489B2 (en) Level shifting circuit
CN101553878B (zh) 包含并联连接的基准磁隧道结以提供最优基准阻抗的磁隧道结反熔丝电路
CN105573456B (zh) 半导体装置
JPWO2010147029A1 (ja) 半導体デバイス
JP4199765B2 (ja) 高電圧スイッチング回路
US20250104785A1 (en) Non-volatile memory circuit and method
US9082498B2 (en) N-well switching circuit
JP5308721B2 (ja) レベルシフト回路
US20120081165A1 (en) High voltage tolerative driver
US7764108B2 (en) Electrical fuse circuit
JP2001067893A (ja) 電気フューズ素子を備えた半導体集積回路装置
US20210090621A1 (en) Bit line logic circuits and methods
US9479169B1 (en) Control circuit applied in e-fuse system and related method
US7453725B2 (en) Apparatus for eliminating leakage current of a low Vt device in a column latch
JP2009283602A (ja) 不揮発性半導体メモリ
JP2017028073A (ja) 集積回路
US7379358B2 (en) Repair I/O fuse circuit of semiconductor memory device
US10381087B2 (en) Apparatuses and methods for transistor protection by charge sharing
KR101210285B1 (ko) 전기적인 퓨즈 프로그래밍을 이용한 1ｔ-ｓｒａｍ의 리던던시 제어 회로
TW201505032A (zh) 用於半導體裝置的冗餘評估電路

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150908

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160825

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20160826

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160830

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20161129

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161130

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20161216

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170110

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170208

R150 Certificate of patent or registration of utility model

Ref document number: 6092427

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees