KR101557812B1 - N-웰 스위칭 회로 - Google Patents
N-웰 스위칭 회로 Download PDFInfo
- Publication number
- KR101557812B1 KR101557812B1 KR1020157021577A KR20157021577A KR101557812B1 KR 101557812 B1 KR101557812 B1 KR 101557812B1 KR 1020157021577 A KR1020157021577 A KR 1020157021577A KR 20157021577 A KR20157021577 A KR 20157021577A KR 101557812 B1 KR101557812 B1 KR 101557812B1
- Authority
- KR
- South Korea
- Prior art keywords
- pmos transistor
- well
- voltage
- gate
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0072—Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/742,964 US8787096B1 (en) | 2013-01-16 | 2013-01-16 | N-well switching circuit |
| US13/742,964 | 2013-01-16 | ||
| PCT/US2014/011138 WO2014113295A1 (en) | 2013-01-16 | 2014-01-10 | N-well switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20150097815A KR20150097815A (ko) | 2015-08-26 |
| KR101557812B1 true KR101557812B1 (ko) | 2015-10-06 |
Family
ID=50031588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157021577A Expired - Fee Related KR101557812B1 (ko) | 2013-01-16 | 2014-01-10 | N-웰 스위칭 회로 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US8787096B1 (enExample) |
| EP (1) | EP2946474B1 (enExample) |
| JP (1) | JP6092427B2 (enExample) |
| KR (1) | KR101557812B1 (enExample) |
| CN (1) | CN104937848B (enExample) |
| WO (1) | WO2014113295A1 (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8787096B1 (en) | 2013-01-16 | 2014-07-22 | Qualcomm Incorporated | N-well switching circuit |
| US9082498B2 (en) * | 2013-08-08 | 2015-07-14 | Qualcomm Incorporated | N-well switching circuit |
| TWI739734B (zh) | 2015-02-23 | 2021-09-21 | 紐西蘭商藍瑟科技紐西蘭有限公司 | 用於將甲烷轉化為產物之重組產醋酸細菌 |
| CN105049029B (zh) * | 2015-07-06 | 2018-05-04 | 上海巨微集成电路有限公司 | 一种pmos管衬底切换电路 |
| JP6905518B2 (ja) | 2015-10-13 | 2021-07-21 | ランザテク・ニュージーランド・リミテッド | エネルギー発生発酵経路を含む遺伝子操作細菌 |
| KR20180127632A (ko) | 2015-12-03 | 2018-11-29 | 란자테크 뉴질랜드 리미티드 | 가스 발효 아세토젠에서의 효율을 개선하기 위한 아르기닌 보충 |
| KR20180118651A (ko) | 2016-02-01 | 2018-10-31 | 란자테크 뉴질랜드 리미티드 | 통합형 발효 및 전해 공정 |
| EP3420089B1 (en) | 2016-02-26 | 2021-12-29 | LanzaTech NZ, Inc. | Crispr/cas systems for c-1 fixing bacteria |
| US9570192B1 (en) | 2016-03-04 | 2017-02-14 | Qualcomm Incorporated | System and method for reducing programming voltage stress on memory cell devices |
| AU2019218389B2 (en) | 2018-02-12 | 2024-09-05 | Lanzatech, Inc. | A process for improving carbon conversion efficiency |
| AU2019257224B2 (en) | 2018-04-20 | 2024-12-19 | Lanzatech, Inc. | Intermittent electrolysis streams |
| CN113225056A (zh) * | 2021-05-21 | 2021-08-06 | 上海韦尔半导体股份有限公司 | 一种控制电路、电路控制方法及电子产品 |
| US12212315B1 (en) * | 2023-01-04 | 2025-01-28 | Cadence Design Systems, Inc. | Interface device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050068069A1 (en) | 2003-09-30 | 2005-03-31 | Sheng-Hua Chen | Input/output buffer |
| US20050128670A1 (en) | 2003-12-12 | 2005-06-16 | Sheng-Hua Chen | Input/output buffer protection circuit |
| US20090261865A1 (en) | 2008-04-17 | 2009-10-22 | Ronald Pasqualini | High voltage CMOS output buffer constructed from low voltage CMOS transistors |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4670668A (en) | 1985-05-09 | 1987-06-02 | Advanced Micro Devices, Inc. | Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up |
| KR0169157B1 (ko) * | 1993-11-29 | 1999-02-01 | 기다오까 다까시 | 반도체 회로 및 mos-dram |
| JP3264622B2 (ja) | 1996-07-16 | 2002-03-11 | 株式会社東芝 | 半導体装置 |
| US5844425A (en) | 1996-07-19 | 1998-12-01 | Quality Semiconductor, Inc. | CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations |
| JP4105833B2 (ja) * | 1998-09-09 | 2008-06-25 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| TW453032B (en) * | 1998-09-09 | 2001-09-01 | Hitachi Ltd | Semiconductor integrated circuit apparatus |
| US6452858B1 (en) * | 1999-11-05 | 2002-09-17 | Hitachi, Ltd. | Semiconductor device |
| US6377112B1 (en) | 2000-12-05 | 2002-04-23 | Semiconductor Components Industries Llc | Circuit and method for PMOS device N-well bias control |
| US6573134B2 (en) * | 2001-03-27 | 2003-06-03 | Sharp Laboratories Of America, Inc. | Dual metal gate CMOS devices and method for making the same |
| US7218151B1 (en) * | 2002-06-28 | 2007-05-15 | University Of Rochester | Domino logic with variable threshold voltage keeper |
| US7038274B2 (en) * | 2003-11-13 | 2006-05-02 | Volterra Semiconductor Corporation | Switching regulator with high-side p-type device |
| KR100728950B1 (ko) * | 2004-03-11 | 2007-06-15 | 주식회사 하이닉스반도체 | 내부전압 발생장치 |
| FR2894373B1 (fr) * | 2005-12-07 | 2008-01-04 | Atmel Corp | Cellule anti-fusible autonome |
| US7355437B2 (en) * | 2006-03-06 | 2008-04-08 | Altera Corporation | Latch-up prevention circuitry for integrated circuits with transistor body biasing |
| US7330049B2 (en) * | 2006-03-06 | 2008-02-12 | Altera Corporation | Adjustable transistor body bias generation circuitry with latch-up prevention |
| TWI451697B (zh) * | 2006-05-03 | 2014-09-01 | Synopsys Inc | 極低功率類比補償電路 |
| US7800179B2 (en) * | 2009-02-04 | 2010-09-21 | Fairchild Semiconductor Corporation | High speed, low power consumption, isolated analog CMOS unit |
| CN101997305B (zh) | 2009-08-26 | 2013-04-10 | 安凯(广州)微电子技术有限公司 | 一种反向电压保护电路及功率管装置 |
| US8787096B1 (en) | 2013-01-16 | 2014-07-22 | Qualcomm Incorporated | N-well switching circuit |
-
2013
- 2013-01-16 US US13/742,964 patent/US8787096B1/en active Active
-
2014
- 2014-01-10 JP JP2015552832A patent/JP6092427B2/ja not_active Expired - Fee Related
- 2014-01-10 EP EP14702369.1A patent/EP2946474B1/en not_active Not-in-force
- 2014-01-10 WO PCT/US2014/011138 patent/WO2014113295A1/en not_active Ceased
- 2014-01-10 KR KR1020157021577A patent/KR101557812B1/ko not_active Expired - Fee Related
- 2014-01-10 CN CN201480004776.9A patent/CN104937848B/zh active Active
- 2014-08-29 US US14/472,953 patent/US9252765B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050068069A1 (en) | 2003-09-30 | 2005-03-31 | Sheng-Hua Chen | Input/output buffer |
| US20050128670A1 (en) | 2003-12-12 | 2005-06-16 | Sheng-Hua Chen | Input/output buffer protection circuit |
| US20090261865A1 (en) | 2008-04-17 | 2009-10-22 | Ronald Pasqualini | High voltage CMOS output buffer constructed from low voltage CMOS transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104937848B (zh) | 2017-12-05 |
| WO2014113295A1 (en) | 2014-07-24 |
| US20140198588A1 (en) | 2014-07-17 |
| EP2946474B1 (en) | 2016-07-27 |
| US20140369152A1 (en) | 2014-12-18 |
| US8787096B1 (en) | 2014-07-22 |
| CN104937848A (zh) | 2015-09-23 |
| EP2946474A1 (en) | 2015-11-25 |
| US9252765B2 (en) | 2016-02-02 |
| KR20150097815A (ko) | 2015-08-26 |
| JP6092427B2 (ja) | 2017-03-08 |
| JP2016511933A (ja) | 2016-04-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| A302 | Request for accelerated examination | ||
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| PA0302 | Request for accelerated examination |
St.27 status event code: A-1-2-D10-D17-exm-PA0302 St.27 status event code: A-1-2-D10-D16-exm-PA0302 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| FPAY | Annual fee payment |
Payment date: 20180628 Year of fee payment: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
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| FPAY | Annual fee payment |
Payment date: 20190624 Year of fee payment: 5 |
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| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
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| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20211001 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
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| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20211001 |